SP7800AJN 查看數據表（PDF） - Signal Processing Technologies
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SP7800AJN Datasheet PDF : 13 Pages
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maximum system accuracy, both should be well–
isolated from digital supplies with wide load varia-
tions.
To limit the effects of digital switching elsewhere in a
system on the analog performance of the system, it
often makes sense to run a separate +5V supply
conductor from the supply regulator to any analog
components requiring +5V, including the SP7800A.
If the SP7800A traces cannot be separated back to the
power supply terminals, and therefore share the same
trace as the logic supply currents, then a 10 Ohm
isolating resistor should be used between the board
supply and pin 24 (VDA) and its bypass capacitors to
keep VDA glitch–free. The VS pins (23 and 24) should
be connected together and bypassed with a parallel
combination of a 6.8µF Tantalum capacitor and a
0.1µF ceramic capacitor located close to the converter
to obtain noise-free operation. (See Figure 1). Noise
on the power supply lines can degrade converter
performance, especially noise and spikes from a
switching power supply. Appropriate supplies or
filters must be used.
The GND pins (4 and 13) are also separated internally,
and should be directly connected to a ground plane
under the converter. A ground plane is usually the best
solution for preserving dynamic performance and
reducing noise coupling into sensitive converter cir-
cuits. Where any compromises must be made, the
common return of the analog input signal should be
referenced to pin 4, AGND, on the SP7800A, which
prevents any voltage drops that might occur in the
power supply common returns from appearing in
series with the input signal.
Coupling between analog input and digital lines should
be minimized by careful layout. For instance, if the
lines must cross, they should do so at right angles.
Parallel analog and digital lines should be separated
from each other by a pattern connected to common.
If external full scale and offset potentiometers are
used, the potentiometers and related resistors should
be located as close to the SP7800A as possible.
“Hot Socket” Precaution
Two separate +5V VS pins, 23 and 24, are used to
minimize noise caused by digital transients. If one pin
is powered and the other is not, the SP7800A may
draw excessive current. In normal operation, this is not
a problem because both pins will be soldered together.
However, during evaluation, incoming inspection,
repair, etc., where the potential of a “Hot Socket”
exists, care should be taken to apply power to the
SP7800A only after it has been socketed.
Minimizing “Glitches”
Coupling of external transients into an analog-to-
digital converter can cause errors which are difficult to
debug. In addition to the discussions earlier on layout
considerations for supplies, bypassing and grounding,
there are several other useful steps that can be taken to
get the best analog performance out of a system using
R/C
tB
BUSY
t DBC
tC
Converter Acquisition
Mode
Conversion
tAP
Hold Time
Acquisition
Conversion
SYMBOL/PARAMETER
MIN
tDBC BUSY delay from R/C
tB BUSY Low
tAP Aperture Delay
∆tAP Aperture Jitter
tC Conversion Time
TYP
80
2.5
13
150
2.47
Figure 4. Acquisition and Conversion Timing
MAX
150
2.7
2.70
UNITS
ns
µs
ns
ps, rms
µs
SP7800ADS/02
SP7800A 12-Bit 3µs Sampling A/D Converter
8
© Copyright 2000 Sipex Corporation
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