SP784CP 查看數據表（PDF） - Signal Processing Technologies

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SP784CP

Programmable Charge Pump

Signal Processing Technologies 

THEORY OF OPERATION

The SP782/784's charge pump design is based

on Sipex's original patented charge pump de-

sign (5,306,954) which uses a four–phase volt-

age shifting technique to attain symmetrical

10V power supplies. In addition, the SP782/

784 charge pump incorporates a "program-

mable" feature that produces an output of ±10V

or ±5V for VSS and VDD by two control pins, D0

and D1. The charge pump requires external

capacitors to store the charge. Figure 1 shows

the waveform found on the positive and nega-

tive side of capcitor C2. There is a free–running

oscillator that controls the four phases of the

voltage shifting. A description of each phase

follows.

Phase 1 (±10V)

— VSS charge storage — During this phase of

the clock cycle, the positive side of capacitors

Citsh1etrnaansndwsfCietcr2rheaedrdettoionCigt2ir–ao.lulSynidncchaenardCg2teh+deistcocho+anr5gnVee.cotCneldC+ t1ios–

+5V, the voltage potential across capacitor C2

is now 10V.

Phase 1 (±5V)

— VSS & VDD charge storage and transfer —

cWtctooahpia+gtarhr5gcoVteiuht,onoeCrdnC.la+C1Snia1isd–mntdi5husVCelttnra2canschnweaasopfrieutgacrcsehrlieytoeoddntrhtstCoeoi2ntCg+hirt2eiio–saVuiltslnrSyadsSncwsashtinfaotedcrrrgharteeghedddee

to the VDD storage capacitor.

Phase 2 (±10V)

— VSS transfer — Phase two of the clock

connects the negative terminal of C2 to the VSS

storage capacitor and the positive terminal of

C2 to ground, and transfers the generated –l0V

or the generated –5V to C3. Simultaneously,

the positive side of capacitor C 1 is switched to

+5V and the negative side is connected to

ground.

Phase 2 (±5V)

— VSS & VDD charge storage — C1+ is

reconnec

capacitor.

ted

C2+

to

is

VCC to

switched

tor egcrohuanr gdeantdhCe 2–Cis1

connected to C3. The 5V charge from Phase 1 is

now transferred to the VSS storage capacitor.

VSS receives a continuous charge from either C1

or C2. With the C1 capacitor charged to 5V, the

cycle begins again.

Phase 3

— VDD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C1 produces –5V in the negative

terminal of C1, which

side of capacitor C2.

is applied

Since C2+

to

is

the negative

at +5V, the

voltage

output,

Cpo2+teinsticaolnancercotsesdCt2o

is l0V.

ground

For the

so that

5V

the

potential on C2 is only +5V.

Phase 4

— VDD transfer — The fourth phase of the

clock connects the negative terminal of C2 to

ground and transfers the generated l0V or the

generated 5V across C2 to C4, the VDD storage

capacitor. Again, simultaneously with this, the

positive side of capacitor C1 is switched to +5V

and the negative side is connected to ground,

and the cycle begins again.

Since both VDD and VSS are separately gener-

ated from VCC in a no–load condition, VDD and

aVpSpSrowaicllhebsethsaytmgmeneetrriactaelV. O– flrdoemr

charge

V+ will

pump

show

a decrease in the magnitude of V– compared to

V+ due to the inherent inefficiencies in the

design.

VCC = +5V

+

C1 –

–5V

+5V

+

C2 –

–5V

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 2. Charge Pump Phase 1 for ±10V.

VCC = +5V

+

C1 –

–5V

+5V

+

C2 –

C4

+ – VDD Storage Capacitor

– + VSS Storage Capacitor

C3

Figure 3. Charge Pump Phase 1 for ±5V.

SP782/SP784 DS/08

SP782/784 Programmable Charge Pump

9

© Copyright 2000 Sipex Corporation

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