SP8057DG 查看數據表（PDF） - Signal Processing Technologies
零件编号
产品描述 (功能)
生产厂家
SP8057DG Datasheet PDF : 4 Pages
| |||
ADVANCED
SP8057
PIN ASSIGNMENTS
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
Vs
GND
GK
HL
EI
FJ
SW1
SW2
RF-
RF+
A
B
C
D
WRF
VCC
Pin Function
Reference voltage. Bypass to GND with ceramic capacitor 0.1uF
Ground pin
Output of GK channel (sum of G + K sensor signals)
Output of HL channel (sum of H + L sensor signals)
Output of EI channel (sum of E + I sensor signals)
Output of FJ channel (sum of F + J sensor signals)
Logic input of Gain Controller. Allows three states – low, high, and middle - Z
Logic input of Gain Controller. Allows three states – low, high, and middle - Z
Output of RF- channel. RF- = - 0.5 x (A + B +C + D)
Output of RF+ channel. RF+ = 0.5 x (A + B + C + D)
Output of A channel
Output of B channel
Output of C channel
Output of D channel
Output of WRF channel. WRF = 4 x (A + B + C + D)
Supply voltage. Bypass to GND with ceramic capacitor 0.1uF
BOARD LAYOUT AND GROUNDING
To obtain the best performance from the SP8057, a printed circuit board with ground plane is
required. High quality, low series resistance ceramic 0.1uF bypass capacitors should be used at
the Vcc and Vs pins (pins 1 and 16). These capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypassing capacitors must be kept short and
should be made as wide as possible.
Rev 0.3 (01-20-04)
SP8057 – High Speed 11-Channel PDIC
SIPEX RESERVES THE RIGHT TO MAKE CHANGES TO THIS DATASHEET. CALL FOR UPDATES: 1-978-667-8700.
SIPEX CONFIDENTIAL, ADVANCED & PROPRIETARY. DO NOT DISTRIBUTE OR
COPY
page 2 of 4
Share Link: 