SP8852DKGHCAR 查看數據表（PDF） - Zarlink Semiconductor Inc

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SP8852DKGHCAR

1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER

Zarlink Semiconductor Inc 

SP8852D

PIN DESCRIPTION

PIN

1,2,3,4,5,6,7,8,9,10,11,40,41,42,43,44

13, 14 (RF INPUT)

17 (LOCK DETECT INPUT)

18 (C–LOCK DETECT)

19 (Rset)

20 (CP OUTPUT)

21 (CP REF)

22

23

24 =Fpd if Pin 23 is HI

=Fref if Pin 23 is LO

25 =Fref if Pin 23 is HI

=Fpd if pin 23 is LO

27 (Reference Oscillator. Capacitor)

28 (Ref IN/XTAL)

29,30,31,32,33,34,35,36,37

38 (Address Input)

39 (Strobe)

DESCRIPTION

These are the inputs to the 16 bit data bus. When Pin 38=HI the data goes to the

buffers for the A counter, M counter and PD Gain. When Pin 38=LO the data goes

to the buffers for the Ref counter and the Phase Detector State (see table 3.)

Open circuit=1 (high) on these pins. Data is transparent from pins to the selected

buffers when Pin 39 (strobe) is HI and frozen in buffers when Pin 39 is LO.

Balanced inputs to the RF pre–amplifier. For single ended operation the signal is

AC coupled into pin 13 with pin 14 AC decoupled to ground (or vice–versa.) Pins

13 and 14 are internally DC biased.

A current sink into this pin is enabled when the lock detect circuit indicates lock.

Used to give an external indication of phase lock.

A capacitor connected to this point determines the lock detect integrator time

constant and can be used to vary the sensitivity of the phase lock indicator.

An external resistor from Pin 19 to VCC sets the charge pump output current.

The phase detector output is a single ended charge pump sourcing or sinking

current to the inverting input of an external loop filter. The direction is controlled by

bit 12 of the reference word. For bit 12=1 and Fpd or RF phase leads Ref phase

Pin 20 will sink current. (see table 2).

Connected to the non–inverting input of the loop filter to set the optimum DC bias.

Not Connected.

Not Connected

RF divider output pulses. Fpd=RF input frequency/(M.N+A). Pulse width=8

RF input cycles (1 cycle of the divide by 8 prescaler output).

Reference divider output pulses. Fref=Reference input frequency/R. Pulse width

=high period of Ref input.

Leave open circuit if an external reference is used. See Fig. 5 for typical

connection for use as an onboard crystal oscillator.

This pin is the input buffer amplifier for an external reference signal. This amplifier

provides the active element if an onboard crystal oscillator is used.

Not Connected.

Controls which buffer the data on the input bus goes to Pin 38=HI sends data to

the RF divider group of functions. Pin 38=LO sends data to the Ref divider group

of functions (see Fig. 6). Open circuit = HI.

When Pin 39 is HI the A, M, and R counters are held in the reset state and the

charge pump output is disabled. The data on the input bus is loaded into the

buffers selected by the Address Input state (Pin 38) when Pin 39 goes low. When

Pin 39 is low the data is fixed in the buffers, the buffers are loaded into the counter

and control register, all the counters are active, and the charge pump is enabled.

Open circuit =HI.

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