SP8854DIGHCAR 查看數據表（PDF） - Zarlink Semiconductor Inc

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SP8854DIGHCAR

1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER

Zarlink Semiconductor Inc 

Bit 15

0

0

1

1

Bit 14

Current Multiplication

Factor

0

1.0

1

1.5

0

2.5

1

4.0

Table 1

] * Pin 19 current

Vcc 1 . 6V

Rset

+ Phase detector gain

p ń Ipin 19(mA)

multiplication factor

2

mA radian

To allow for control direction changes introduced by the

design of the PLL, pin 23 is used to reverse the sense of the

phase detector by transposing the Fpd and Fref connections.

In order that any external phase detector will also be reversed,

the Fpd/Fref outputs are interchanged by pin 23 as shown in

Table 2.

Output for RF Phase Lag

Control direction pin 23

Pin 20

1

Current Source

0

Current Sink

Table 2

SP8854D

The Fpd and Fref signals to the phase detector are available

on pin 24 and 25 and may be used to monitor the frequency

input to the phase detector or used in conjunction with an

external phase detector. The outputs are disabled by taking

pin 22 low. When the Fpd and Fref outputs are to be used at

W high frequencies, an external pull down resistor of minimum

value 330 may be connected to ground to reduce the fall time

of the output pulse.

The charge pump connections to the loop amplifier consist

of the charge pump output and the charge pump reference.

The matching of the charge pump up and down currents will

only be maintained if the charge pump output is held at a

voltage equal to the charge pump reference using an

operational amplifier to produce a virtual earth condition at pin

20.

The lock detect circuit can drive an LED to give visual

indication of phase lock or provide an indication to the control

system if a pull up resistor is used in place of the LED. A small

capacitor connected from the c–lock detector pin to ground

may be used to delay lock detect indication and remove

glitches produced by momentary phase coincidence during

lock up.

40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 PIN

213 212 211 210 29 28 27 26 25 24 23 22 21 20

PHASE

DETECTOR

GAIN

CONTROL

See Table 1

M COUNTER

3 BIT A

COUNTER

Fig. 6 Programming pin allocation

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