SP9502JN 查看數據表（PDF） - Signal Processing Technologies

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SP9502JN

Dual, 12–Bit, Voltage Output D/A Converter

Signal Processing Technologies 

SPECIFICATIONS (continued)

(Typical at 25˚C, TMIN ≤ TA≤TMAX; VDD = +5V, VSS = -5V, VREF = +3V; CMOS logic level digital inputs; specifications apply to all grades unless otherwise noted.)

PARAMETER

MIN. TYP. MAX.

UNITS

CONDITIONS

STABILITY

Gain

15

Bipolar Zero

15

SWITCHING CHARACTERISTICS

tDS Data Set Up Time

140

100

tDN Data Hold Time

0

tWR Write Pulse Width

140

100

tXFER Transfer Pulse Width

140

100

tWC Total Write Command

280

200

POWER REQUIREMENTS

VDD

–J, –K

4

6

VSS

–J, –K

4

6

Power Dissipation

40

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

-J, -K

Storage

Package

_N

_S

0

+70

-60

+150

28–pin Plastic DIP

28–pin SOIC

ppm/˚C

ppm/˚C

ns

ns

ns

ns

ns

mA

mA

mW

°C

°C

tMIN to tMAX

tMIN to tMAX

to rising edge of WR1,

Figure 4

Note 5

+5V, ±3%; Note 4, 5

-5V, ±3%; Note 4, 5

Notes:

1.

2.

3.

4.

Integral Linearity, for the SP9502, is measured as the arithmetic mean value of the magnitudes of

the greatest positive deviation and the greatest negative deviation from the theoretical value for any

given input condition.

Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

1 LSB = 2*VREF/4,096.

VREF = 0V.

5.

The following power up sequence is recommended to avoid latch up: VSS (-5V), VDD (+5V), REFIN.

I0NLE, DLNE Plots

SP9502DS/02

CODE

SP9502 Dual, 12-Bit, Voltage Output D/A Converter

3

+0.25 lsb

DNLE

-0.25 lsb

+0.25 lsb

INLE

-0.25 lsb

4095

© Copyright 1999 Sipex Corporation

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