SPCA514A 查看數據表（PDF） - Unspecified

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SPCA514A

Digital Audio USB Controller

Unspecified 

SPCA514A

2. The flash memory data access must be through by the CPU because the flash memory

data bus is directly connected with the CPU data bus. Therefore there are two type

pseudo DMA operations to access flash memory data to post buffer:

(1) The CPU reads the data register of the post buffer (0X8300) and the hardware

generates a write pulse to flash memory in the same time. The data flow is from post

buffer to flash memory.

(2) The CPU reads the data register of the post buffer and the hardware generates a read

pulse to flash memory in the same time. The data flow is from flash memory to post

buffer.

3. The CPU accesses flash memory data via the register (0X8400) in the direct mode.

The ECC is not generated by hardware in this mode. Therefore all accesses for the flash

memory that do not want to disturb the ECC calculation must be in this mode, for example

the additional data access.

3.5. Post buffer

3.5.1. Buffer Control

There are two 1k-byte deep FIFOs in the device to concurrently handle both incoming

and outgoing data stream in various operation modes and to easily handle data for the

USB host controller. Some detailed information about the FIFO is shown as follows.

OprMode Source

Destination FIFO Size

Note

Idle

None

None

Idle mode

Upload 1 CPU (0X8300) Flash memory The page size of FIFO mode

flash memory

Upload 2 Flash Memory CPU (0X8300) The page size of FIFO mode

flash memory

Upload 3 Flash Memory USB

The page size of Pseudo DMA (2)

flash memory

Upload 4 CPU (0X8300) USB

64 bytes

Bulk IN pipe

Upload 5 USB

CPU (0X8300) 64 bytes

Bulk OUT pipe

 

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