SPCA514A 查看數據表（PDF） - Unspecified

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SPCA514A

Digital Audio USB Controller

Unspecified 

SPCA514A

3.5.6. Upload Mode (5):

When the USB host wants to update the ROM code for the CPU on flash memory, the

“OprMode” field in the register (0X8301) must be set to the value of 0X5. The new ROM

code is transmitted into post buffer from the PC through the Bulk-OUT pipe. Then the

CPU reads the post buffer and update the ROM code on the flash memory. The deep of

post buffer is 64 bytes in this mode.

3.5.7. Upload Mode (6):

When the USB host wants to pseudo write into flash memory by the CPU, the “OprMode”

field in the register (0X8301) must be set to the value of 0X6. The data is transmitted into

post buffer from the PC through the Bulk-OUT pipe. Then the CPU reads the post buffer

and write into the flash memory. The deep of post buffer is 256 bytes in this mode.

3.5.8. Upload Mode (8):

This is a test mode. In this mode, the “OprMode” field in the register (0X8301) must be

set to the value of 0X8. The CPU will write, read back and compare data through post

buffer and the deep of post buffer is 64 bytes in this mode.

3.6. Power Control

To reduce power-consumption during suspend period, the clock pad is disabled during

suspend state. All the internal clocks stop and the SPCA514 can only accept asynchronous

events during the suspend state. Before the SPCA514 returns to normal operational state,

there is an additional state called resume state. During the resume state the clock pad start

oscillation. However, the internal clocks are still masked out to prevent chip malfunction

since during this period the clock is not stable. The following diagram depicts the sequence

for the SCAP514 to enter and get out of the suspend/resume state.

 

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