AN7820 查看數據表（PDF） - Fairchild Semiconductor

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AN7820

EVALUATION BOARD

Fairchild Semiconductor 

This approach is to use a three-bit reconstruction DAC

generated from LSB’s TTL outputs of the last three LSBs.

This circuit is shown in figure 17. When jumpers SJ9-SJ11

are installed, R30-R33 forms a three-bit DAC as shown in

figure 14.

to the ideal step with ±(1/n) LSB of accuracy. In this case, the

ideal step is the average of the step size. Other errors (MC,

transition noise and nonmonotonicity) can be resolved in a

similar way. Figure 15 also gives the identification of each

error from the actual transfer curve.

The output of this three bit reconstruction DAC can be

viewed through the test point STEP with the scope. For this

test, use a function generator for the generators 1 and 2

(HP3325A or equivalent) and set up for a ramp output.

Replace the BPF with an RC low pass filter (1k and 0.01 µF)

to eliminate all high frequency components. Set the slew

rate of this ramp signal to 1 LSB per n conversions (sam-

pling period) for a desired (1/n) test resolution. A minimum

of n = 10 is recommended for this application. The P-P

voltage and the period of the ramp input are then dependent

on the selection of the number of steps (LSBs) within one

ramp’s period. You may need to remove R10 (51 Ω). Set CLK

and CCLK to the same relatively low frequency, approxi-

mately 1 MHz or even slower. Adjust as needed to meet the

tpwH and ts specifications. (See figure 5-6 and table 5.)

The following formulas summarize the criteria for selecting

the analog ramp input signal:

The ramp peak-to-peak voltage:

Vp-p =

m(FSR/1024)

The ramp period: T = (m) ( n) / Fs Where:

m=

desired number of steps

(LSBs) per ramp’s period

Fs =

sampling frequency

FSR =

full scale range (typically

SPT7820/24's FSR is 4 V)

n=

desired test resolution or the num-

ber of conversions/LSB

Figure 15 shows the relationship between the analog input

ramp signal and the resulting three-bit reconstruction DAC. It

shows 16 LSBs of P-P input voltage (i.e., two 8-level steps)

per period. For an ideal ADC and an ideal ramp input, its

digital output code changes state by 1 LSB every (n)th

conversion (dash line in the transfer curve). Any error in the

ADC makes the corresponding output codes change state

before or after the (n)th conversion. This error will translate

into smaller or larger respective step width. The DLE can be

judged visually by comparing the actual step size with respect

Example:

1) SPT7820 is operated at 500 kHz (sampling frequency).

2) (1/10) of the test resolution is desired.

3) The scope is externally triggered to the ramp input. Three

retraces of 8-level steps (or 24 total steps) per ramp’s

period are selected.

What peak-to-peak voltage (V p-p) and period (T) of the ramp

input signal are required to drive the SPT7820?

Answer:

1) Fs = 500 kHz,

2) n = 10 ,

3) m = 24, then V(p-p) = m ( FSR / 1024) = 24( 4 /1024) =

94 mV

and T = (m) ( n) / Fs = (24) (10) / 5000,000 = 480 µsec

Note that the above input signal will only cover 24 parts in

1024 of the FSR. To identify all errors through the full scale

range, slowly sweep the ramp input from -FS to +FS and

observe the output steps for the MC, transition noise, DLE

and non-monotonicity as indicated in the transfer curve

(figure 15 ). Most generators do not have the DC offset

covering the range from +2.5 V to -2.5 V. You may need to

construct an additional circuit using the classical summing

amplifier to DC offset the above ramp input signal.

The synchronous noise in an ADC is the distortion of the

performance of the device when the sampling frequency

varies. (Normally, the DLE can be clearly observed.) This is

usually caused by the digital signals being coupled back,

internally into the analog input signal. This problem is very

common for ADCs using the successive approximation reg-

ister (SAR) architecture. The ADC that possesses this kind

of symptom presents some weak performances at a specific

sampling frequency (within the specified sampling rate), but

shows better results when the sampling frequency is varied

up or down from that weak spot. To verify the synchronous

noise using this set-up, slowly change the sampling fre-

quency and observe the transfer curve, especially the changes

in DLE.

AN7820/24

10

5/22/97

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