AN7820 查看數據表（PDF） - Fairchild Semiconductor
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AN7820 Datasheet PDF : 17 Pages
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Figure 6 - EB7820/24 Timing Diagram Where CCLK is the Same as CLK IN
Figure 7 - EB7820/24 Timing Diagram Where CCLK is 180° Out of Phase From CLK IN
U5, pin 3 N
CLK
(EB7820/24)
CLK IN
(SPT7820/24)
tpd2
tpd3
DATA OUT
(SPT7820/24)
VALID
(N-2)
tpd1
CCLK
(LATCHES)
DATA OUT
(P2)
(N-2)
N+1
N+2
tpwH
tpwL
VALID
(N-1)
ts
(N-1)
VALID
(N)
th
tpd4
(N)
N+3
N+4
VALID
(N+1)
VALID
(N+2)
(N+1)
Table 4 - P2, SPT7820/24 Output Data (Latched) , 26-Pin Female Ribbon Connector
P2 Function
Logic
P2
Function
1
CCLK
TTL
2
DGND
3
N/A
TTL/LO
4
DGND
5
N/A
TTL/LO
6
DGND
7
D0 (LSB)
TTL
8
DGND
9
D1
TTL
10
DGND
11 D2
TTL
12
DGND
13 D3
TTL
14
DGND
15 D4
TTL
16
DGND
17 D5
TTL
18
DGND
19 D6
TTL
20
DGND
21 D7
TTL
22
DGND
23 D8
TTL
24
DGND
25 D9 (MSB)
TTL
26
DGND
Logic
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AN7820/24
5
5/22/97
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