SPT7851 查看數據表（PDF） - Cadeka Microcircuits LLC.
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SPT7851 Datasheet PDF : 9 Pages
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DATA SHEET
SPT7851
Electrical Specifications
(TA = TMIN–TMAX, VDD1 = VDD2 = VDD3 = 3.3V, VREF– = 1.0V, VREF+ = 2.0V, Common Mode Voltage = 1.65V, ƒCLK = 20 MSPS,
Bias1 = 90µA, Bias2 = 9.5µA, Differential Input, Duty Cycle = 50%; unless otherwise noted)
Parameter
DC Accuracy
Resolution
Differential Linearity
Integral Linearity
No Missing Codes
Analog Input
Input Voltage Range (differential)
Common Mode Input Voltage
Input Capacitance
Input Bandwidth (large signal)
Offset (mid-scale)
Gain Error
Reference Voltages
Reference Input Voltage Range
Negative Reference Voltage (VREF–)
Positive Reference Voltage (VREF+)
Common Mode Output Voltage (VCM)
VREF+ Current
VREF– Current
Switching Performance
Maximum Conversion Rate
Pipeline Delay (see Figure 1)
Aperture Delay Time (TAP)
Aperture Jitter Time
Dynamic Performance
Signal-To-Noise Ratio
Effective Number of Bits
Total Harmonic Distortion
Signal-To-Noise and Distortion
Spurious Free Dynamic Range
Differential Phase
Differential Gain
Conditions
VIN+ = VIN- = VCM
VREF+ – VREF–
IO = -1µA
ƒIN = 5MHz
ƒIN = 10MHz
ƒIN = 5MHz
ƒIN = 10MHz
ƒIN = 5MHz
ƒIN = 10MHz
ƒIN = 5MHz
ƒIN = 10MHz
ƒIN = 5MHz
ƒIN = 10MHz
Test Level Min Typ Max Units
10
Bits
V
±0.6
LSB
V
±0.75
LSB
VI
Guaranteed
IV
±0.6 ±1.0 ±1.7 V
IV
1.2 1.65 1.9 V
V
1.4
pF
V
120
MHz
V
±1.0
%FSR
V
0.3
%FSR
IV
0.6 1.0 1.7 V
IV
0.9 1.0 1.3 V
IV
1.9 2.0 2.9 V
VI
1.3 1.65 1.8 V
V
35
µA
V
-25
µA
VI
20
IV
7.5
V
5
V
10
MHz
CLK
ns
ps-rms
VI
57 58
dB
V
58
dB
VI
9.0 9.3
Bits
V
9.0
Bits
VI
-68 -61 dB
V
-60
dB
VI
56 58
dB
V
56
dB
VI
62 70
dB
V
61
dB
V
0.2
deg
V
0.5
%
2
REV. 1B October 2003
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