SPT7851 查看數據表（PDF） - Cadeka Microcircuits LLC.
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SPT7851 Datasheet PDF : 9 Pages
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SPT7851
DATA SHEET
Sampling
Points
N-1
AIN
CLK
DOUT
N
N+1
tAP
N+2
N+6
N+7
N+8
tD
N-2
N-1
N
Figure 1: Timing Diagram
General Description
The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC.
It has a pipelined architecture and incorporates digital error
correction of all 10 bits. This error correction ensures good
linearity performance for input frequencies up to Nyquist.
The inputs are fully differential, making the device insensi-
tive to system-level noise. This device can also be used in a
single-ended mode. (See analog input section.) With the
power dissipation roughly proportional to the sampling rate,
this device is ideal for very low power applications in the
range of 1 to 20 MSPS.
Typical Interface Circuit
The SPT7851 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7851
in normal circuit operation. The following sections provide
a description of the functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
RFIN
Ref- In
(+1.15 V)
Ref+ In
(+2.15 V) +
4.7 µF
4.7 µF
+
.01 µF
11
12
N/C
N/C
90 µA
N/C
GND
9.5 µA
.01 µF
(+1.65 V)
Bias1
Bias2
VCM
GND
51Ω
68 pF
22
VIN+
VIN-
GND
Minicircuit
23
T1-6T
.01 µF
+3.3V
10 µF
+
.01 µF
CLKIN
(3V Logic)
+3.3V
0.1 µF
1
U1
SPT7851
GND
AGND
VDD3 44
DNC
DNC
D0
(LSB)
D1
D2
D3
D4
D5
D6
D7
34
33
FB
+3.3V Digital
Decoupling
Cap
Interfacing
3V Logic
DGND
Note: 1. All VDD1, VDD2 and VDD3 should be tied together.
2. FB = Ferrite Bead; must be placed as close to U1 as possible.
Figure 2: Typical Interface Circuit
REV. 1B October 2003
5
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