MP7226LN 查看數據表（PDF） - Exar Corporation

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MP7226LN

BiCMOS Fixed, Quad, Voltage Output, Single or Dual Supply 8-Bit Digital-to-Analog Converter

Exar Corporation 

MP7226

VDD

VIN

A0

A1

Output

WR

1 of 4

Decoder

To DAC1 Latch Enable

To DAC2 Latch Enable

To DAC3 Latch Enable

To DAC4 Latch Enable

AGND

VSS

Figure 2. Simplified Output Buffer Amplifiers

The amplifiers outputs may be shorted to ground. However,

the power dissipation of the package should not exceed the

maximum limit.

Digital Inputs

All of the digital inputs to this DAC maintain TTL level inter-

face compatibility and can also be driven directly with 5V CMOS

logic inputs. The digital inputs are ESD protected to a rating of

2000 volts.

Digital Interface Logic

The MP7226 allows direct interface to most microprocessor

buses without additional interface circuitry.

Figure 3. shows the input control logic circuit diagram and

Table 1. shows the control logic truth table and operation for

WR, A1, A0. The address lines A0, and A1 determine which

DAC will accept the input data. The WR input determines

whether the selected DAC is transparent (output follows the in-

put), latched, or no operation. The WR input will also inhibit

power on reset of the DAC latches to 0, if its initial state = 0 after 5

µs of power.

Figure 4. shows the write cycle timing diagram. When the WR

signal is low, the input latch of the selected DAC is transparent,

and the DAC’s output corresponds to the value present on the

data bus. On some data buses, data is not always valid for the

entire period that the WR signal is low and can cause unwanted

data at the output. Ensuring that the write pulse (WR) conforms

to the data hold time, (t4) spec will prevent this problem.

Figure 3. Input Control Logic

WR A1 A0

H

X

X

L

L

L

L

L

L

L

H

L

H

L

L

H

H

Operation

No Operation;

Device Not Selected

DAC 1 Transparent

DAC 1 Latched

DAC 2 Transparent

DAC 3 Transparent

DAC 4 Transparent

Table 1. Truth Table

Address

WR

Data

tAS

tAH

5V

tWR

tDS

VINH

VINL

0V

5V

0V

tDH

5V

0V

NOTE: When the WR signal is low, the input latch of the se-

lected DAC is transparent and any invalid data at this time will

cause erroneous output.

Figure 4. Write Cycle Timing Diagram

Rev. 2.00

8

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