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SST36VF1602 Datasheet PDF : 26 Pages
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16 Megabit Concurrent SuperFlash
SST36VF1601 / SST36VF1602
Advance Information
CE#,whicheveroccursfirst.DuringtheEraseoperation,the the rising edge of sixth WE# (or CE#) pulse. See Figure 8
only valid read is Toggle Bits or Data# Polling. See Table 4 for Data# Polling (DQ7) timing diagram and Figure 20 for a
for the command sequence, Figure 10 for timing diagram,
and Figure 22 for the flowchart. Any commands issued
flowchart.
1
during the Chip-Erase operation are ignored.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any con-
Write Operation Status Detection
secutive attempts to read DQ6 will produce alternating 1’s
2
The SST36VF1601/1602 provide one hardware and two and 0’s, i.e., toggling between 1 and 0. When the internal
software means to detect the completion of a Write (Pro- Program or Erase operation is completed, the DQ6 bit will
gram or Erase) cycle, in order to optimize the system write
stop toggling. The device is then ready for the next
3
cycle time. The hadware detection uses the Ready/Busy# operation.TheToggleBit(DQ6) isvalidaftertherisingedge
(RY/BY#) output pin. The software detection includes two of fourth WE# (or CE#) pulse for Program operation. For
status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
Sector-, Block- or Chip-Erase, the Toggle Bit (DQ6) is valid
4
End-of-Writedetectionmodeisenabledaftertherisingedge aftertherisingedgeofsixthWE#(orCE#)pulse.SeeFigure
of WE#, which initiates the internal Program or Erase 9forToggleBittimingdiagramandFigure21foraflowchart.
operation.
5
Data Protection
The actual completion of the nonvolatile write is asynchro-
The SST36VF1601/1602 provide both hardware and soft-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ7) or Toggle Bit (DQ6) read may
ware features to protect nonvolatile data from inadvertent
writes.
6
be simultaneous with the completion of the Write cycle. If
this occurs, the system may possibly get an erroneous
result, i.e., valid data may appear to conflict with either DQ7
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
7
or DQ6. In order to prevent spurious rejection, if an errone-
5 ns will not initiate a write cycle.
ous result occurs, the software routine should include a loop
to read the accessed location an additional two (2) times. If
VDD Power Up/Down Detection: The Write operation is
8
bothreadsarevalid,thenthedevicehascompletedthewrite inhibited when VDD is less than 1.5V.
cycle, otherwise the rejection is valid.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high
will inhibit the Write operation. This prevents inadvertent
9
Ready/Busy# (RY/BY#)
writes during power-up or power-down.
The SST36VF1601/1602 includes a Ready/Busy# (RY/
BY#) output signal. During any SDP initiated operation, e.g.,
Hardware Block Protection
10
Erase, Program, CFI or ID Read operation, RY/BY# is
The SST36VF1601/1602 provide a hardware block protec-
actively pulled low, indicating a SDP controlled operation is
in Progress. The status of RY/BY# is valid after the rising
tion which protects the outermost 4 KWords in the larger
bank.The block is protected when WP# is held low. See
11
edge of fourth WE# (or CE#) pulse for Program operation.
Figures 1 and 2 for Block-Protection location.
For Sector-, Block- or Bank-Erase, the RY/BY# is valid after
the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an
A user can disable block protection by driving WP# high
12
open drain output that allows several devices to be tied in thus allowing erase or program of data into the protected
parallel to VDD via an external pull up resistor. Ready/Busy# sectors. WP# must be held high prior to issuing the write
is in high impedance whenever OE# or CE# is high or RST#
command and remain stable until after the entire write
13
is low.
operation has completed.
Data# Polling (DQ7)
When the SST36VF1601/1602 are in the internal Program
Hardware Reset (RESET#)
When the RESET# input pin is held low for at least TRP, any
14
operation,anyattempttoreadDQ7 willproducethecomple- in progress operation will terminate and return to Read
ment of the true data. Once the Program operation is
completed, DQ7 will produce true data. The device is then
mode. If the part is not busy, a minimum period of TRHR is
required after RESET# is driven high before a valid read can
15
readyforthenextoperation.DuringinternalEraseoperation, take place. If the part is busy, poll RY/BY#, Data# Polling,
any attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling (DQ7) is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
or Toggle Bit to determine when the device is ready.
Initiating a reset during a Write operation (Program or
Erase) is not recommended. Data may be in an undeter-
16
Block- or Chip-Erase, the Data# Polling (DQ7) is valid after
mined state.
© 2000 Silicon Storage Technology, Inc.
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