SST39VF040-55-4I-MKE 查看數據表（PDF） - Silicon Storage Technology

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SST39VF040-55-4I-MKE

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash

Silicon Storage Technology 

Data Sheet

512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040

SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040

TOP VIEW (balls facing down)

6

A2

A8 A9 A11 NC1 OE# A10 CE#

5

A1 A17 A14 A13

DQ7 DQ5 DQ6

4

A0 VDD WE#

3

DQ3 DQ4

CE# A16 A18

2

DQ2 VSS

VSS A12 A15 A7

1

A0 DQ0 DQ1

A6 A5 A4 NC2 A3 A2 A1

FIGURE

AB C D E F G H J

Note: For SST39LF020, ball B3 is "No Connect"

For SST39LF010, balls B3 and A5 are "No Connect"

5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit

TABLE 2: Pin Description

Symbol

Pin Name

Functions

AMS1-A0

Address Inputs

To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the

sector. During Block-Erase AMS-A16 address lines will select the block.

DQ7-DQ0

Data Input/output

To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE#

Chip Enable

To activate the device when CE# is low.

OE#

Output Enable

To gate the data output buffers.

WE#

Write Enable

To control the Write operations.

VDD

Power Supply

To provide power supply voltage: 3.0-3.6V for SST39LF512/010/020/040

2.7-3.6V for SST39VF512/010/020/040

VSS

Ground

NC

No Connection

Unconnected pins.

1. AMS = Most significant address

AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040

T2.1 1150

TABLE 3: Operation Modes Selection

Mode

Read

Program

Erase

CE#

VIL

VIL

VIL

OE#

VIL

VIH

VIH

Standby

Write Inhibit

Product Identification

Software Mode

VIH

X

X

VIL

X

X

VIL

VIL

1. X can be VIL or VIH, but no other value.

WE#

VIH

VIL

VIL

DQ

DOUT

DIN

X1

X

High Z

X

High Z/ DOUT

VIH

High Z/ DOUT

VIH

Address

AIN

AIN

Sector address,

XXH for Chip-Erase

X

X

X

See Table 4

T3.4 1150

©2010 Silicon Storage Technology, Inc.

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