SST45LF010 查看數據表（PDF） - Silicon Storage Technology

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SST45LF010

1 Mbit Serial Flash

Silicon Storage Technology 

Data Sheet

1 Mbit Serial Flash

SST45LF010

WP#

VDD

CE#

SCK

1

8

2

7

Top View

3

6

4

5

RST#

VSS

SO

SI

372 ILL F01.6

8-LEAD SOIC

WP# 1

VDD 2

CE# 3

SCK 4

Top View

8 RST#

7 VSS

6 SO

5 SI

372 ILL F01a.2

8-CONTACT WSON

FIGURE 2: PIN ASSIGNMENTS

TABLE 2: PIN DESCRIPTION

Symbol Pin Name

SCK Serial Clock

SI

SO

CE#

WP#

Serial Data Input

Serial Data Output

Chip Enable

Write Protect

RST# Reset

VDD

Power Supply

VSS

Ground

Functions

To provide the timing of the serial interface. Commands, addresses, or input data are latched

on the rising edge of the clock input, while output data is shifted out on the falling edge of the

clock input.

To transfer commands, addresses, or data serially into the device. Inputs are latched on the

rising edge of the serial clock.

To transfer data serially out of the device.

Data is shifted out on the falling edge of the serial clock.

The device is enabled by a high to low transition on CE#.

To protect the device from unintentional Write (Erase or Program) operations. When WP# is

low, all Erase and Program commands are ignored. When WP# is high, the device may be

erased or programmed. This pin has an internal pull-up and could remain unconnected when

not used.

A high to low transition on RST# will terminate any operation in progress and reset the internal

logic to the standby mode. The device will remain in the reset condition as long as the RST# is

low. Operations may only occur when RST# is high. This pin has an internal pull-up and could

remain unconnected when not used.

To provide power supply (3.0-3.6V).

T2.5 372

©2003 Silicon Storage Technology, Inc.

4

S71128-04-000 3/03 372

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