ST1284 查看數據表（PDF） - STMicroelectronics

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ST1284

Parallel port single termination network with ±15 kV ESD protection

STMicroelectronics 

Technical information

3

Technical information

ST1284

3.1

Frequency behavior of data and strobe signals

Figure 5. Measurement conditions

TRACKING

GENERATOR

50Ω

Vg

+5V

SPECTRUM

ANALYSER

ST1284

50Ω

Vin

Vout

Figure 6. Typical frequency response curve

for data and STROBE signal

0.00 dB

-5.00

-10.00

-15.00

-20.00

-25.00

-30.00

1

3

F (MHz)

10

30

100

300

1,000

3.2

ESD protection

In addition to the requirements of termination and EMC compatibility, computing devices are

required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and

is already in place in Europe. This test requires that a device tolerates ESD events and

remain operational without user intervention.

The ST1284-01A8 is particularly optimized to perform ESD protection. ESD protection is

based on the use of device which clamps at:

Vouput = VBR + Rd · IPP

This protection function is split in 2 stages. As shown in Figure 7, the ESD strikes are

clamped by the first stage S1 and then its remaining overvoltage is applied to the second

stage through the resistor R. Such a configuration makes the voltage very low at the output.

Figure 7. ST1284 ESD clamping behavior

ESD Surge

Rg

S1

R

S2

Rd

Vinput

Rd

VBR

Voutput

VBR

ST1284-xxA8

Rload

Device

to be

protected

6/10

Doc ID 6976 Rev 4

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