ST1284 查看數據表（PDF） - STMicroelectronics

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ST1284

Parallel port single termination network with ±15 kV ESD protection

STMicroelectronics 

ST1284

Technical information

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give

the typical dynamic resistance value Rd.

By taking into account these following hypothesis:

Rt>Rd, Rg>Rd and Rload>Rd, it gives these formulas:

Vinput = -R----g----⋅---V----B----R-----+-----R----d----⋅---V----P----P--

Rg

Voutput = R-----t---⋅---V----B----R----+-----R-----d----⋅---V----i--n----p---u----t

Rt

The results of the calculation done for VPP = 8 kV, Rg = 330 Ω (IEC 61000-4-2 standard),

VBR = 7 V (typ.) and Rd = 1 Ω (typ.) give:

– Vinput = 31.2 V

– Voutput = 7.95 V

This confirms the very low remaining voltage across the device to be protected. It is also

important to note that in this approximation the parasitic inductance effect was not taken into

account. This could be few tenths of volts during few ns at the input side. This parasitic effect

is not present at the output side due the low current involved after the resistance R.

The measurements done here after show very clearly (Figure 9) the high efficiency of the

ESD protection:

– no influence of the parasitic inductances on Vout stage

– Voutput clamping voltage very close to VBR (positive strike) and -VF (negative

strike)

Figure 8. Measurement conditions

ESD

SURGE

Vinput

ST1284

Voutput

Figure 9. Remaining voltage at the input and output of the device during a ±16 kV

ESD surge (IEC 61000-4-2)

Doc ID 6976 Rev 4

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