AD568SQ 查看數據表（PDF） - Analog Devices
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AD568SQ Datasheet PDF : 14 Pages
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AD568
BIPOLAR ZERO ERROR: The deviation of the analog output
from the ideal half-scale output of 0 V (or 0 mA) for bipolar
mode when only the MSB is on (100 . . .00) is called bipolar
zero error.
GAIN ERROR: The difference between the ideal and actual
output span of FS –1 LSB, expressed in % of FS, or LSB, when
all bits are on.
GLITCH IMPULSE: Asymmetrical switching times in a DAC
give rise to undesired output transients which are quantified by
their glitch impulse. It is specified as the net area of the glitch in
nV-sec or pA-sec.
COMPLIANCE VOLTAGE: The range of allowable voltage at
the output of a current-output DAC which will not degrade the
accuracy of the output current.
SETTLING TIME: The time required for the output to reach
and remain within a specified error band about its final value,
measured from the digital input transition.
0.8
0.6
0.4
0
50
100
150
200
250
TIME – ns
Figure 2. Glitch Impulse
+15V
–15V
0.2µF
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
3
–15V 22 0.1µF
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16 NC
10
SPAN 15 NC
11
THCOM 14
100pF
12
VTH 13
RTH
1kΩ
0.1µF
FERRITE BEADS
STACKPOLE 57-1392
OR
AMIDON FB-43B-101
OR EQUIVALENT
ANALOG
OUTPUT
REXT
(OPTIONAL)
ANALOG
SUPPLY GROUND
ANALOG
GND PLANE
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
Connecting the AD568
+5V
UNBUFFERED VOLTAGE OUTPUT
Unipolar Configuration
Figure 3 shows the AD568 configured to provide a unipolar 0 to
+1.024 V output range. In this mode, the bipolar offset termi-
nal, Pin 21, should be grounded if not used for offset trimming.
The nominal output impedance of the AD568 with Pin 19
grounded has been trimmed to 100 Ω, ± 1%. Other output im-
pedances can be generated with an external resistor, REXT, be-
tween Pins 19 and 20. An REXT equalling 300 Ω will yield a
total output resistance of 75 Ω, while an REXT of 100 Ω will pro-
vide 50 Ω of output resistance. Note that since the full-scale
output current of the DAC remains 10.24 mA, changing the
load impedance changes the unbuffered output voltage accord-
ingly. Settling time and full-scale range characteristics for these
load impedances are provided in the specifications table.
Figure 3. Unipolar Output Unbuffered 0 V to +1.024 V
+15V
–15V
0.2µF
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
3
–15V 22 0.1µF
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
100pF
10
SPAN 15
11
THCOM 14
12
VTH 13
0.1µF
ANALOG
OUTPUT
ANALOG
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
Bipolar Configuration
Figure 4 shows the connection scheme used to provide a bipolar
output voltage range of 1.024 V. The bipolar offset (–0.512 V)
occurs when all bits are OFF (00 . . . 00), bipolar zero (0 V) oc-
curs when the MSB is ON with all other bits OFF (10 . . . 00),
and full-scale minus 1 LSB (0.51175 V) is generated when all
bits are ON (11 . . . 11). Figure 5 shows an optional bipolar
mode with a 2.048 V range. The scale factor in this mode will
not be as accurate as the configuration shown in Figure 4, be-
cause the laser-trimmed resistor RL is not used.
+5V
Figure 4. Bipolar Output Unbuffered ±0.512 V
Figure 4 also demonstrates how the internal span resistor may
be used to bias the VTH pin (Pin 13) from a 5 V supply. This
eliminates the requirement for an external RTH in applications
that do not require the precision span resistor.
–4–
REV. A
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