AD568SQ 查看數據表（PDF） - Analog Devices
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AD568SQ Datasheet PDF : 14 Pages
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AD568
+15V
–15V
0.2µF
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
3
–15V 22 0.1µF
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16 NC
10
SPAN 15 NC
11
THCOM 14
100pF
12
VTH 13
RTH
1kΩ
0.1µF
ANALOG
OUTPUT
ANALOG
GND PLANE
DIGITAL
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
SUPPLY
GROUND
full scale at the DAC output. Note: this may slightly compro-
mise the bipolar zero trim.
DIGITAL
INPUTS
1 BIT 1
24
2 MSB
23
3 AD568 22
4
IBPO 21
5
IOUT 20
6
RL 19
7
ACOM 18
8
LCOM 17
9
16
10
15
11
14
12
BIT 12
LSB
13
GAIN
20Ω
VCC
5.11kΩ
75Ω
ZERO
20kΩ
ANALOG
OUTPUT
(–0.512 TO
0.512V)
VEE
Figure 7. Bipolar Unbuffered Gain and Zero Adjust
+5V
Figure 5. Bipolar Output Unbuffered ±1.024 V
Optional Gan and Zero Adjustment
The gain and offset are laser trimmed to minimize their effects
on circuit performance. However, in some applications, it may
be desirable to externally reduce these errors further. In those
cases, the following procedures are suggested.
UNIPOLAR MODE: (Refer to Figure 6)
Step 1 – Set all bits (BIT 1–BIT 12) to Logic “0” (OFF)—note
the output voltage. This is the offset error.
Step 2 – Set all bits to Logic “1” (ON). Adjust the gain trim re-
sistor so that the output voltage is equal to the desired full scale
minus 1 LSB plus the offset error measured in step 1.
Step 3 – Reset all bits to Logic “0” (OFF). Adjust the offset
trim resistor for 0 V output.
DIGITAL
INPUTS
1 BIT 1
24
2 MSB
23
3 AD568 22
4
IBPO 21
5
IOUT 20
6
RL 19
7
ACOM 18
8
LCOM 17
9
16
10
15
11
14
12
BIT 12
LSB
13
GAIN
20Ω
5.11kΩ
100Ω
OFFSET
ANALOG
OUTPUT
(0 TO 1.024V)
Figure 6. Unbuffered Unipolar Gain and Zero Adjust
BIPOLAR MODE (Refer to Figure 7)
Step 1 – Set bits to offset binary “zero” (10 . . . 00). Adjust the
zero resistor to produce 0 V at the DAC output. This removes
the bipolar zero error.
Step 2 – Set all bits to Logic “1” (ON). Adjust gain trim resistor
so the output voltage is equal to the desired full-scale minus
l LSB .
Step 3 – (Optional) If precise trimming of the bipolar offset is
preferred to trimming of bipolar zero: set all bits to Logic “0”
(OFF). Trim the zero resistor to produce the desired negative
BUFFERED VOLTAGE OUTPUT
For full-scale outputs of greater than 1 V, some type of external
buffer amplifier is required. The AD840 fills this requirement
perfectly, settling to 0.025% from a 10 V full-scale step in less
than 100 ns.
A 1 kΩ span resistor has been provided on chip for use as a
feedback resistor in buffered applications. Using RSPAN (Pins 15,
16) introduces a 100 mW code-dependent power source onto
the chip which may generate a slight degradation in linearity.
Maximum linearity performance can be realized by using an ex-
ternal span resistor.
+15V –15V
0.2µF
0.1µF
DIGITAL
INPUTS
1
+15V 24
0.1µF
2
REFCOM 23
0.1µF
3
–15V 22
4
IBPO 21
5
IOUT 20
6 AD568 RL 19
7
ACOM 18
8
LCOM 17
9
SPAN 16
5pF
10
SPAN 15
11
THCOM 14
100pF
12
VTH 13
RTH
1kΩ
–VS
100Ω
+VS
AD840
ANALOG
OUTPUT
ANALOG
GND PLANE
ANALOG
SUPPLY
GROUND
DIGITAL
GND PLANE
DIGITAL
SUPPLY
GROUND
AMPLIFIER NOISE GAIN: 11
+5V
Figure 8. Unipolar Output Buffered 0 to –10.24V
Unipolar Inverting Configuration
Figure 8 shows the connections for producing a – 10.24 V full-
scale swing. This configuration uses the AD568 in the current
output mode into a summing junction at the inverting input ter-
minal of the external op amp. With the load resistor RL
grounded, the DAC has an output impedance of 100 Ω. This
produces a noise gain of 11 from the noninverting terminal of
the op amp, and hence, satisfies the stability criterion of the
AD840 (stable at a gain of 10). The addition of a 5 pF compen-
REV. A
–5–
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