ST7282 查看數據表（PDF） - STMicroelectronics

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ST7282

ROM FROM EPROM

STMicroelectronics 

ST7282A5 - ST7282B5 - ROM FROM EPROM

2 IMPLEMENTATION REMARKS OF THE DEDICATIONS

In this chapter the options of the dedications, which are implemented are described. The dedications are

described in detail in the target specs of the dedications. In case of discrepancies between this specifica-

tion and the specs. of the dedications, this specification is valid.

2.1 Core

2.1.1 Oscillator

The oscillator can be used with quartz or ceramic resonator. The pins OSCIN and OSCOUT permit con-

nection to the on chip clock oscillator circuit. OSCIN is the input, OSCOUT the clock oscillator output. A

quartz or a ceramic resonator can be connected to these pins. Two external ceramic capacitors of 22pF

connect the oscillator pins to ground. Also an external system clock can be applied to the oscillator input

OSCIN.

2.1.2 External reset input RESET

Low level active external reset input with Schmitt-Trigger characteristic. A pull-up resistor of typically

300kΩ ( 200kΩ - 500kΩ ) is integrated. This pin is resetting the I/O ports immediately without any need of

a clock.

2.1.3 Stack

The Stack is located at 3FFH and may go down to 300H.

2.1.4 Interrupts

I1 is connected to IOPorts A ... H (start address FFFAH )

I2 is connected to RDS GRP & BLK SYNC (block interrupt) ( start address FFF8H )

I3 is connected to SIO ( start address FFF6H )

I4 is connected to Timer ( start address FFF4H )

I5 is connected to ADC (start address FFF2H )

I6 is connected to RDS GRP & BLK SYNC (bit interrupt) (start address FFF0H )

If more then 1 input pin of a group, connected to the same interrupt, is selected as interrupt input with pul-

lup, all selected inputs are "AND" connected.

WARNING :

Read modify write instructions may clear interrupt flags of dedications unintentionally if the interrupt flag is

set after the read and before the write. Operations on control registers of dedications should be done with

sufficient timing distance to interrupt events.

2.1.5 Miscellaneous register( 0026h )

Read/Write

Reset Value: 0000 0000 ( 00h )

This register is a various 8-Bit register where only 3 bits are used for interrupt and slow mode.

– b6 = INTP: Interrupt Positive allows to select the I1 line triggering mode in conjunction with INTN. It can

only be modified when the I bit of the CCR is set.

– b5 = INTN: Interrupt Negative allows to select the I1 line triggering mode in conjunction with INTP. It can

only be modified when the I bit of the CCR is set.

– b1 = SM: Slow Mode. Setting this bit to "1" enables Slow Mode, thus reducing power consumption. In

this mode, an extra divider by 64 is added in the clock circuitry. In Halt Mode SM bit is automatically

reset.Registers of all RDS-Modules should not be accessed during slow mode.

Family

ST7

Issuer Ref.

PG-RO

Chrono

97115

7282A5B5

March 26, 1997

Previous Ref

Edition

Target C

Page 11/23

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