ST7571 查看數據表（PDF） - Sitronix Technology Co., Ltd.
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ST7571 Datasheet PDF : 76 Pages
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ST7571
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Power Supply Pin Description
Name
I/O
Description
VDD1
Power supply for digital circuit.
Power
If VDD1 is the same level as VDD2, they can be connected together by FPC.
VDD2
Power Power supply for analog circuit (booster).
VDD3
Power supply for sensitive circuit (internal Vref regulator).
Power
VDD3 is the same level as VDD2, and they should be connected together by FPC.
VSS1
Power Ground for digital circuit. VSS1, VSS2 & VSS3 should be connected together by FPC.
VSS2
Power Ground for analog circuit (booster), it should be connected together by FPC.
VSS3
Power Ground for sensitive circuit (Vref regulator), it should be connected together by FPC.
6.2 LCD DRIVER SUPPLY
LCD Driver Supply Pin Description
Name
I/O
Description
V0 is the LCD driving voltage for common circuits at negative frame.
V0O
V0O is the output of V0 regulator. V0S is the feedback of V0 regulator.
V0I
Power V0I is the V0 input of common circuits.
V0S
Be sure that: V0 ≥ VG > VM > VSS ≥ XV0 (under operation).
V0O, V0I & V0S should be connected together by FPC.
XV0O
XV0I
XV0S
Power
XV0 is the LCD driving voltage for common circuits at positive frame.
XV0O is the output of XV0 regulator. XV0S is the feedback of XV0 regulator.
XV0I is the XV0 input of common circuits.
XV0O, XV0I & XV0S should be connected together by FPC.
VG is the LCD driving voltage for segment circuits.
VGO
VGI
VGS
Power
A storage capacitor on FPC or system for VG is required.
VGO is the output of VG regulator. VGS is the feedback of VG regulator.
VGI is the VG input of segment circuits.
VGO, VGI & VGS should be connected together by FPC.
Be aware that: 1.8V ≤ VG < VDD2.
VMO is the output of VM, which is the LCD driving voltage for common circuits.
A storage capacitor on FPC or system for VM is required.
Be aware that: 0.7V < VM < VDD2.
VMO
When the internal power circuit is active, the VG and VM are generated according to the bias
Power
setting as shown below:
LCD bias
VG
VM
1/N bias
(2/N) x V0
(1/N) x V0
NOTE: N = 5 to 12
Ver 1.5a
10/76
2009/7/21
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