ST8024CD 查看數據表（PDF） - STMicroelectronics

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ST8024CD

COM/SEG LCD Driver

STMicroelectronics 

ST8024

Figure 3: Definition of output and input transition times

FUNCTIONAL DESCRIPTION

Throughout this document it is assumed that the reader is familiar with ISO7816 terminology.

POWER SUPPLY

The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals

interfacing with the system controller are referred to VDD, therefore VDD should also supply the system

controller. All card reader contacts remain inactive during power-on or power-off.

The internal circuits are maintained in the reset state until VDD reaches Vth2 +Vhys2 and for the duration of

the internal Power-on reset pulse, tW (see Fig.4). When VDD falls below Vth2, an automatic deactivation of

the contacts is performed.

A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The DC/DC

converter should be supplied separately by VDDP and PGND. Due to the possibility of large transient

currents, the two 100 nF capacitors of the DC/DC converter should be located as near as possible to the

IC and have an ESR less than 100 mΩ.

The DC/DC converter functions as a voltage doubler or a voltage follower according to the respective

values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV).

The DC/DC converter function changes as follows:

VCC = 5 V and VDDP > 5.8 V; voltage follower

VCC = 5 V and VDDP < 5.7 V; voltage doubler

VCC = 3 V and VDDP > 4.1 V; voltage follower

VCC = 3 V and VDDP < 4.0 V; voltage doubler.

Supply voltages VDD and VDDP may be applied to the IC in any sequence.

After powering the device, OFF remains LOW until CMDVCC is set HIGH.

During power off, OFF falls LOW when VDD is below the falling threshold voltage.

VOLTAGE SUPERVISOR

- WITHOUT EXTERNAL DIVIDER ON PIN PORADJ

The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8ms (tW) is used

internally to keep the IC inactive during power-on or power-off of the VDD supply (see Fig.4).

As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the command

lines. This state also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys2.

When VDD falls below Vth2, a deactivation sequence of the contacts is performed.

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