ST8024S 查看數據表（PDF） - Sitronix Technology Co., Ltd.

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ST8024S

COM/SEG LCD Driver

Sitronix Technology Co., Ltd. 

ST8024S

DI7

S/C

DI6-DI0

XCK

Y1 -Y240

"H" dual mode operation is selected.

Ÿ Refer to section 6.2.2.

Dual mode data input pin

Ÿ According to the data shift direction of the data shift register, data can be input starting

from the 121st bit.

When the chip is used in dual mode, DI7 will be pulled down.

When the chip is used in single mode, DI7 won't be pulled down.

Ÿ Refer to section 6.2.2.

Segment mode/common mode selection pin

Ÿ When set to LGND level "L", common mode is set.

Not used

Ÿ Connect DI6-DI0 to LGND or VDD, avoiding floating.

Not used

Ÿ XCK is pulled down in common mode, so connect to LGND or open.

LCD drive output pins

Ÿ Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or VSS) is

selected and output.

Ÿ Table of truth values is shown in "TRUTH TABLE" in Functional Operations.

6.2

Functional Operations

6.2.1 Truth table

(Segment Mode)

FR

LATCH DATA

L

L

L

H

H

L

H

H

X

X

/DISPOFF

H

H

H

H

L

LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)

V43

VSS

V12

V0

VSS

(Common Mode)

FR

LATCH DATA

/DISPOFF

LCD DRIVE OUTPUT VOLTAGE LEVEL (Y1-Y240)

L

L

H

V43

L

H

H

V0

H

L

H

V12

H

H

H

VSS

X

X

L

VSS

NOTES:

1. VSS < V43 < V12 < V0

2. L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care

3. "Don't care" should be fixed to "H" or "L", avoiding floating.

There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.

Supply regular voltage which is assigned by specification for each power pin.

Ver 0.39

Page 8/27

2008/05/05

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