STK14CA8 查看數據表（PDF） - Simtek Corporation
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STK14CA8 Datasheet PDF : 17 Pages
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STK14CA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK14CA8-25
MIN MAX
12
tAVAV
tAVAV
tWC
Write Cycle Time
25
13
tWLWH
tWLEH
tWP
Write Pulse Width
20
14
tELWH
tELEH
tCW
Chip Enable to End of Write
20
15
tDVWH
tDVEH
tDW
Data Set-up to End of Write
10
16
tWHDX
tEHDX
tDH
Data Hold after End of Write
0
17
tAVWH
tAVEH
tAW
Address Set-up to End of Write
20
18
tAVWL
tAVEL
tAS
Address Set-up to Start of Write
0
19
tWHAX
tEHAX
20
t e,g
WLQZ
tWR
Address Hold after End of Write
tWZ
Write Enable to Output Disable
0
10
21
tWHQX
tOW
Output Active after End of Write
3
Notes
g: If W is low when E goes low, the outputs remain in the high-impedance state.
h: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
ADDRESS
12
tAVAV
14
tELWH
E
STK14CA8-35
MIN MAX
35
25
25
12
0
25
0
0
13
3
19
tWHAX
STK14CA8-45
MIN MAX
45
30
30
15
0
30
0
0
15
3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
PREVIOUS DATA
20
tWLQZ
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledh,f
ADDRESS
18
tAVEL
12
tAVAV
14
tELEH
19
tEHAX
E
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
December 2005
6
Document Control #ML0022 rev 1.3
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