STK14CA8-NF25ITR 查看數據表（PDF） - Simtek Corporation
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STK14CA8-NF25ITR Datasheet PDF : 21 Pages
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SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
1
2
tAVAVc
3
tAVQVd
4
5
tAXQXd
6
7
tELQV
tELEHc
tAVQVd
tGLQV
tAXQXd
tELQX
tEHQZe
tACS
Chip Enable Access Time
tRC
Read Cycle Time
tAA
Address Access Time
tOE
Output Enable to Data Valid
tOH
Output Hold after Address Change
tLZ
Address Change or Chip Enable to
Output Active
tHZ
Address Change or Chip Disable to
Output Inactive
8
tGLQX
tOLZ
Output Enable to Output Active
9
tGHQZe
tOHZ
Output Disable to Output Inactive
10
tELICCHb
tPA
Chip Enable to Power Active
11
tEHICCLb
tPS
Chip Disable to Power Standby
Note c:
Note d:
Note e:
Note f:
W must be high during SRAM READ cycles.
Device is continuously selected with E and G both low
Measured ± 200mV from steady state output voltage.
HSB must remain high during READ and WRITE cycles.
STK14CA8
STK14CA8-25
MIN MAX
25
25
25
12
3
STK14CA8-35
MIN MAX
35
35
35
15
3
STK14CA8-45
MIN MAX
45
45
45
20
3
UNITS
ns
ns
ns
ns
ns
3
3
3
ns
10
13
15
ns
0
0
0
ns
10
13
15
ns
0
0
0
ns
25
35
45
ns
SRAM READ CYCLE #1: Address Controlledc,d,f
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E and G Controlledc,f
ADDR ESS
E
27
G
DQ (D ATA OUT)
ICC
6
tELQ X
2
tE LE H
1
tEL Q V
3
tAV QV
8
tG L Q X
4
tG L QV
10
tELI CC H
ST AND BY
AC T IVE
Document Control #ML0022 Rev 2.1
5
Jan, 2008
29
tEHAX
11
tEHI CC L
7
tEHQ Z
9
tGH Q Z
DAT A VAL ID
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