STK14CA8-NF25ITR 查看數據表（PDF） - Simtek Corporation
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STK14CA8-NF25ITR Datasheet PDF : 21 Pages
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STK14CA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
STK14CA8-25
MIN MAX
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
tWLQZe, g
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
tWP Write Pulse Width
tCW Chip Enable to End of Write
tDW Data Set-up to End of Write
tDH Data Hold after End of Write
tAW Address Set-up to End of Write
tAS Address Set-up to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
25
20
20
10
0
20
0
0
10
3
Note g: If W is low when E goes low, the outputs remain in the high-impedance state.
Note h: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledg,h
ADDRESS
12
tAVAV
14
tELWH
E
STK14CA8-35
MIN MAX
35
25
25
12
0
25
0
0
13
3
19
tWHAX
STK14CA8-45
MIN MAX
45
30
30
15
0
30
0
0
15
3
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
SRAM WRITE CYCLE #2: E Controlledg,h
ADDRESS
12
tAVAV
18
tAVEL
14
tELEH
19
tEHAX
E
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
Document Control #ML0022 Rev 2.1
6
Jan, 2008
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