STK14C88-5 查看數據表（PDF） - Cypress Semiconductor
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STK14C88-5 Datasheet PDF : 17 Pages
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STK14C88-5
SRAM Write Cycle
Parameter
Cypress
Parameter
Alt
tWC
tAVAV
tPWE
tWLWH, tWLEH
tSCE
tELWH, tELEH
tSD
tDVWH, tDVEH
tHD
tWHDX, tEHDX
tAW
tAVWH, tAVEH
tSA
tAVWL, tAVEL
tHA
tWHAX, tEHAX
tHZWE [11,12]
tWLQZ
tLZWE [11]
tWHQX
Switching Waveforms
ADDRESS
CE
WE
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
35 ns
Min
Max
35
25
25
12
0
25
0
0
13
5
45 ns
Min
Max
45
30
30
15
0
30
0
0
15
5
Figure 10. SRAM Write Cycle 1: WE Controlled [13, 14]
tWC
tSCE
tHA
tAW
tSA
tPWE
DATA IN
DATA OUT
ADDRESS
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
Figure 11. SRAM Write Cycle 2: CE Controlled [13, 14]
tWC
tSA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
13. HSB must be high during SRAM WRITE cycles.
14. CE or WE must be greater than VIH during address transitions.
Document Number: 001-51038 Rev. **
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 10 of 17
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