STK14CA8 查看數據表（PDF） - Cypress Semiconductor
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STK14CA8 Datasheet PDF : 16 Pages
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STK14CA8
SRAM WRITE Cycles #1 and #2
Symbols
NO.
#1
#2 Alt.
Parameter
STK14CA8-25 STK14CA8-35 STK14CA8-45
Units
Min Max Min Max Min Max
12
tAVAV
tAVAV
tWC Write Cycle Time
25
35
45
ns
13
tWLWH tWLEH
tWP Write Pulse Width
20
25
30
ns
14
tELWH
tELEH
tCW Chip Enable to End of Write
20
25
30
ns
15
tDVWH tDVEH
tDW Data Setup to End of Write
10
12
15
ns
16
tWHDX tEHDX
tDH Data Hold after End of Write
0
0
0
ns
17
tAVWH
tAVEH
tAW Address Setup to End of Write
20
25
30
ns
18
tAVWL
tAVEL
tAS Address Setup to Start of Write
0
0
0
ns
19
tWHAX tEHAX
tWR Address Hold after End of Write
0
0
0
ns
20
tWLQZ[5,7]
tWZ Write Enable to Output Disable
10
13
15 ns
21
tWHQX
tOW Output Active after End of Write
3
3
3
ns
ADDRESS
E
W
DATA IN
DATA OUT
Figure 8. SRAM WRITE Cycle #1: W Controlled[7,8]
12
tAVAV
14
tELWH
19
tWHAX
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
16
tWHDX
21
tWHQX
ADDRESS
E
Figure 9. SRAM WRITE Cycle #2: E Controlled[7,8]
12
tAVAV
18
tAVEL
14
tELEH
19
tEHAX
W
DATA IN
17
tAVEH
13
tWLEH
15
tDVEH
DATA OUT
HIGH IMPEDANCE
Notes
7. If W is low when E goes low, the outputs remain in the high impedance state.
8. E or W must be ≥ VIH during address transitions.
DATA VALID
Document Number: 001-51592 Rev. **
16
tEHDX
Page 6 of 16
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