STK15C88(2007) 查看數據表（PDF） - Simtek Corporation
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STK15C88 Datasheet PDF : 14 Pages
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SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
tWLQZh, i
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC Write Cycle Time
tWP Write Pulse Width
tCW Chip Enable to End of Write
tDW Data Set-up to End of Write
tDH Data Hold after End of Write
tAW Address Set-up to End of Write
tAS Address Set-up to Start of Write
tWR Address Hold after End of Write
tWZ Write Enable to Output Disable
tOW Output Active after End of Write
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
ADDRESS
12
tAVAV
14
tELWH
E
18
tAVWL
W
17
tAVWH
13
tWLWH
DATA IN
DATA OUT
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledj
ADDRESS
E
18
tAVEL
12
tAVAV
14
tELEH
STK15C88
(VCC = 5.0V ± 10%)
STK15C88-25 STK15C88-45
UNITS
MIN MAX MIN MAX
25
45
ns
20
30
ns
20
30
ns
10
15
ns
0
0
ns
20
30
ns
0
0
ns
0
0
ns
10
15
ns
5
5
ns
19
tWHAX
16
tWHDX
21
tWHQX
19
tEHAX
W
DATA IN
DATA OUT
17
tAVEH
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
16
tEHDX
Document Control #ML0016 Rev 0.3
5
February, 2007
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