STLC5432 查看數據表（PDF） - STMicroelectronics
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STLC5432 Datasheet PDF : 46 Pages
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STLC5432
XCLK (respectively Transmit Data and its clock
associated). Frame and multiframe generated by
the transmitter of the circuit are processed by the
receiver of the circuit, without encoding and de-
coding.
4.4 LOOPBACK 4
LP4 Command replaces Data in with Data out
near of DIN and DOUT pins (See LP4R register).
5 FRAME ALIGNMENT
Time slot 0 is used for the synchronization
(G.706). At software Reset Frame and Multiframe
are lost and a new research of FAS and MFAS is
launched.
5.1 LOSS OF FRAME ALIGNMENT
Frame alignment will be assumed to have been
lost :
– either when three consecutive incorrect frame
alignment signals have been received,
– or when bit 2 in time slot 0 in odd frames has
been received with an error, i.e. at 0, on three
consecutive occasions,
– or when 915 errored CRC blocks out of 1000
have been detected.
5.2 FRAME ALIGNMENT RECOVERY
Frame alignment will be assumed recovered
when the following sequence is detected:
– Detection of the correct Frame Alignment Sig-
nal, FAS
– detection of bit 2 of 32nd byte after FAS, at 1.
– detection of the correct Frame Alignment sig-
nal in the 64th byte after the first FAS de-
tected.
5.3 MULTIFRAME ALIGNMENT RECOVERY
Multiframe Alignment will be assumed recovered
when at least two valid multiframe alignment sig-
nals MFAS have been detected within 8 ms.
Table 1: CRC4 Multiframe Structure G.704
Sub
Multiframe
Frame
1
2
0
C1
0
1
0
1
2
C2
I
3
0
1
4
C3
5
1
1
6
C4
7
0
1
8
C1
9
1
1
10
C2
II
11
1
1
12
C3
13
E1
1
14
C4
15
E2
1
TIME SLOT ZERO BIT NUMBERS
3
4
5
6
7
8
0
1
1
0
1
1
A
Sa4
Sa5
Sa61
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa62
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa63
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa64
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa61
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa62
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa63
Sa7
Sa8
F
A
S
A
Sa4
Sa5
Sa64
Sa7
Sa8
FAS:
Frame Alignment Signal in each even Time Slot.
MFAS:
Multi Frame Alignment Signal 0 0 1 0 1 1
E1–E2:
CRC4 error Indication bits
C1 to C4: Cyclic Redundancy Check 4 (CRC4) bits
A:
Remote Alarm Indication
Sa4 to Sa8: Five bits in each odd Time Slot
Sa61 to Sa64: ETSI bits
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