STLC5432 查看數據表（PDF） - STMicroelectronics

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STLC5432

2Mbit CEPT & PRIMARY RATE CONTROLLER DEVICE

STMicroelectronics 

STLC5432

PIN DESCRIPTION

Name

VCCD1

VCCD2

VCCA

GNDD

GNDA

LI1

LI2

VT

L01

L02

XTAL1

XTAL2

HCR

LCR

BRDO

RCLO

BRDI

RCLI

BXDO

BXDI

DOUT

DIN

Pin Type

Function

18

I Positive power supply inputs for the digital (VCCD1) and analog (VCCA) sections and for

17

I microprocessor interface signals (VCCD2). They must be +5 Volts and must be directly

34

I connected together.

1

I Negative power supply pins which must be connected together close to the device. All

44

I digital and analog signals are referred to these pins, which are normally at the system

ground.

40

42

I

I

Receive HDB3 signal differential inputs from the line transformer.

41

O Positive power supply output for fixing reference voltage to the receive transformer.

Typical value is 2.375V

36

O Transmit HDB3 signal differential outputs to the line transformer.When used with an

37

O appropriate transformer, the line signal conforms to the output specifications in CCITT

with a nominal pulse amplitude of 3 volts for a 120Ω load on line side.

15

I The master clock input which requires either a parallel resonance crystal to be tied

between this pin and XTAL2, or a clock input from a stable source. This clock does

not need to be synchronized to the system clock.

Crystal specifications = 32764 kHz ± 50 ppm parallel resonant; RS ≤ 20Ω loaded with

33pF to GND each side.

16

O The output of the crystal oscillator, which should be connected to one end of the

crystal if used.

19

O High clock received, bit clock. When the device has recovered the clock from the

HDB3 signal, HCR signal is synchronized to the remote circuit. The HCR frequency is

either 8192kHz if 8MCR bit of CR1 Register is put to 1 or 4096 kHz if 8MCR is set to

0.

20

O Low clock received, frame clock. When the device has recovered the clock from the

HDB3 signal, LCR signal is synchronized to the remote entity.

The LCR frequency is 8 kHz if 8KCR bit is set to 1, or 4 kHz if 8KCR bit is set to 0.

When the remote clock is not recovered, HCR and LCR frequency are synchronized

to master clock (16384 kHz).

HCR and LCR can be used by the system in Terminal Mode.These two clocks can be

used by the transmit function of the device.

12

O Binary Receive Data Output, 2048 kbit/s or 64kbit/s.

14

O Receive Clock output, 2048 kHz or 64kHz.

After decoding, Binary Data and clock associated are provided for different

applications.

10

I Binary Receive Data Input. 2048 kbit/s.

9

I Receive Clock Input 2048 kHz.

22

O Binary Transmit Data Output, 2048 kbit/s or output clock at 64kHz.

Before encoding Binary Data is provided to different applications (Optical Interface for

instance). Local clock is associated to this data.

33

I This binary signal can replace BXD internal signal to be encoded if SELEX bit (CR1

Register) is set to 1.

11

O Data Output. 30 B+D primary access data received from the line.Data can be shifted

out from the tristate output DOUT at the LCLK frequency on the rising edges during

all the time slots,except Time Slot Zero in accordance with TSOE bit (CR1Register).

NB : If parallel micro-interface is selected, DOUT is at high impedance after Reset.

DOUT is at low impedance after writing CR4 register.

3

I Data Input : 30B+D primary access data to transmit to the line.Data can be shifted in

at the LCLK frequency on the falling edges during all the time slots, except Time Slot

Zero, in accordance with TSOE bit (CR1 Register).

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