STLC5432 查看數據表（PDF） - STMicroelectronics
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STLC5432 Datasheet PDF : 46 Pages
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STLC5432
PIN DESCRIPTION (continued)
Name
LCLK
LFSR
LFSX
AL0,
AL1
Pin Type
Function
23
I Local Clock : this clock input determines the data shift rate on the two digital
multiplexes. This clock frequency can be indifferently 2048, 4096, 8192 or 16384kHz.
Data Out and Data In rate is always 2048 kbit/s when Serial Interface microprocessor:
an internal automatic mechanism divides by two the frequency if 4096 kHz.
24
I Local Frame Synchronization for the Receiver. This clock input defines the start of the
frame on the digital multiplex Data (pin DOUT). This clock frequency can be
indifferently 8 kHz or a submultiple of 8 kHz.
25
I Local Frame Synchronization for the Transmitter. This clock input defines the start of
the frame on the digital multiplex Data (pin DIN). This clock frequency can be
indifferently 8 kHz or a submultiple of 8 kHz.
If submultiple of 8 kHz, LFSX defines the start of even frame on DIN. The TSO of this
even frame will contain the Frame Alignment Signal (FAS) on the line.
32
O Alarm 0 Output, alarm 1 Output. These pins are open drain outputs which are
31
O normally in high impedance state.
AL1 AL0 Alarm definitions
Z
0Volt
Z
0Volt
Z
Z
0Volt
0Volt
Frame or Multiframe recovered,
A bit received is 0.
Frame or Multiframe recovered,
A bit received is 1
Frame and Multiframe lost, AIS
Alarm Indication Signal is detected.
Frame and Multiframe lost, AIS
Alarm Indication Signal is not detected.
DPI
38
SA/RESET
2
P0, P1
39, 43
I DPI input: The internal DPLL is synchronized either by the signal applied on DPI input
(if DPIS bit of CR5 register is = 0) or by the 2MHz clock recovered from the line.
I Stand Alone : When this pin is connected to 5 Volts, the device works without
microprocessor. The configuration is given by the values per default of programmable
registers. BRDI and BXDI must not be used.
RESET: When this pin is put to 5 Volts during 100 ns at least every programmable
register is reset (value per default). When this pin is set at zero Volt, the type of
microprocessor is selected by P0, P1 pins.
I Processor interface. These two input pins define the microprocessor interface
chosen.
P1 P0
Microprocessor Interface
-----------------------------------------------------------------------------------
0
0
Serial Microprocessor Interface
0
1
ST9 Microprocessor Interface
1
0
Multiplexed Motorola processor interface
1
1
Multiplexed Intel processor interface
AS/ALE
13
CS
35
R/W/WR
26
DS/RD
21
A/D0 to A/D7 4 to 7;
27 to 30
INT
8
I Address Strobe/Address Latch Enable. Input
I Chip Select. A high level on this input selects the PRCD for a read write operation.
I Read/Write/Write Data. Input.
I Data Strobe/Read Data. Input.
I/O Address/Data 0 to 7. Input-Output.
O Interrupt Request. The signal is activated low when the PRCD requests an interrupt. It
is an open drain output.
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