STLC5432 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
STLC5432 Datasheet PDF : 46 Pages
| |||
Using both options allow the reception of a signal
attenuated up to 12dB at 1024kHz.
The Clock recovery is performed by a first PLL
that guaranties the CCITT I431 requirements for
the allowed Jitter, see Figure 23, this clock, RCL,
is used internally and as local clock.
A second DPLL starting from this RCL clock at-
tenuate the Jitter, to fulfil the CCITT I431, see fig-
ure 8, this DPLL generate HCR, bit clock, and
LCR frame clock, practically without Jitter.
1.2 Transmitter
The line driver outputs are designed to drive the
suitable transformer mentioned in the previous
section. The transformer results in a signal ampli-
tude of 3 volts on the line which meet G.703 pulse
shape for a 120 ohm load (2.37 volt for a 75
ohms load).
A special test mode is provided to check the
pulse template according to the CCITT mask by
using the configuration register CR3 (ASP).
When the ALS command is valid, consecutive
logical ”ones” are transmitted on the line.
When APS command is valid, consecutive 1, 0,
1... 1, 0, 1, 0... are transmitted on the line.
2 CODING
2.1 HDB3/BIN DECODING
The two constituents of the data signal are de-
coded and the binary Receive Data Signal (BRD)
is processed by the next functions.
2.2 BIN/HDB3 ENCODING
The binary transmit data signal (BXD) is encoded.
The entire data stream, including all the time
slots, is scanned for an occurence of four con-
secutive zeros.
Such occurence is replaced by the appropriate
HDB3 code.
3. BINARY INPUT-OUTPUT
STLC5432 can directly interface binary data
stream by means of the 6 dedicated pins:
BRDO, RCLO, BRDI, RCLI, BXDO and BXDI.
This allows the use of STLC5432 also for particu-
lar cases as for optical fiber or for different pur-
poses. The functions of these 6 pins are defined
by the SIG bit (SIGR register).
3.1 SIG = 0
When the bit SIG = 0 the binary data are ex-
changed at 2048KHz and the 6 extra pins are de-
fined hereafter.
3.1.1 Extra pins for receive data
The BRDO and RCLO output pins deliver respec-
STLC5432
tively BRD binary receive data at 2048kb/s and
the remote clock recovered at 2048kHz.
Two BRDI and RCLI input pins can receive exter-
nal binary receive data at 2048kb/s and the re-
ceive clock associated at 2048kHz.
The SELER command replaces BRD internal sig-
nal with BRDI signal.
3.1.2 Extra pins for transmit data
The transmit binary data output pin BXDO deliv-
ers transmit binary data BXD.
Input pin BXDI can receive external binary trans-
mit data.
The SELEX command replaces BXD internal sig-
nal with BXDI signal.
3.2 SIG = 1
When SIG = 1, a signaling channel at 64 kb/s is
implemented.
3.2.1 Extra pins for Receive data
BRDO and RCLO output pins deliver respectively
receive data at 64kb/s selected by an internal
Time Slot Assigner and the receive clock associ-
ated at 64kHz. In this case, BRDI and RCLI are
not used.
3.2.2 Extra pins for Transmit Data
Output BXDO delivers the 64kHz clock for an ex-
ternal application. This external entity delivers
data at 64kb/s on the rise edge of the clock.
Input BXDI shifts data at 64 kb/s on the fall edge
of the 64kHz clock.
The same Time Slot Assigner is used by transmit-
ter and receiver (See SIGR Register).
4 LOOPBACK
4.1 LOOPBACK 1
When LP1 Command is valid (LP1 bit high, see
CRC3 register), output data signal replaces input
data signal. Then, the recovery clock function pro-
vides the local clock. The loopback is transparent
if AIS is at 0. If AISX is at 1, consecutive logical
”ones” are transmitted on the line.
4.2 LOOPBACK 2
LP2 Command (LP2 bit high, CR3 register) re-
places BXD and XCLK signals (respectively Bi-
nary Transmit Data and transmit clock) with BRD
and RCLK (respectively Binary Receive data and
its clock recovered).
4.3 LOOPBACK 3
LP3 Command (LP3 bit high, CR3 register) re-
places BRD and RCLK (respectively Binary Re-
ceive Data and its clock recovered) with BXD and
9/46
Share Link: 