ICS9158-05M 查看數據表（PDF） - Integrated Circuit Systems
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ICS9158-05M Datasheet PDF : 7 Pages
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ICS9158-05
Advanced Information
Pin Configuration
Functionality
VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated
OE PD# FS1 FS0
1100
1101
CPU
Ratio
14/4xX1
14/3xX1
X1,X2,
REF
(MHz)
14.318
14.318
CPU
(0:2)
(MHz)
50
66.7
BUS
(0:4)
(MHz)
25
33.3
1 1 1 0 42/10xX1 14.318 60
30
1 1 1 1 (STOP) 14.318 Low Low
1
0
X
X
(PWR
DOWN)
Low
*Low *Low
0XXX
-
Tristate Tristate Tristate
24-Pin SOIC
PD# forces all outputs low and powers-down the oscillator and PLL
circuitry, minimizing power consumption. In order to ensure glitch-free start
and stop of the CPU and BUS clocks, PD# should be asserted after the
CPU and BUS clocks have stopped, and be deasserted 10ms (maximum
PLL lock time) prior to starting the clocks.
OE PD# FLOPPY (MHz) KEYBD (MHz)
11
24
12
Pin Descriptions for ICS9158-05
10
0X
Low
Tristate
Low
Tristate
PIN NUMBER PIN NAME
1
REFCLK
TYPE
OUT
14.318 clock output.
DESCRIPTION
2
X2
OUT Crystal connection, which includes output crystal load capacitance.
3
X1
4
VDD
5
GND
6
KEYBD
IN
PWR
PWR
OUT
Crystal connection, which includes crystal load capacitance and feedback bias
for a nominal 14.31818 MHz parallel-resonance 12pF crystal.
Digital POWER SUPPLY.
Digital GROUND.
12 MHz keyboard clock output.
7
FLOPPY
8
BUS0
9
AGND
10
OE
11
BUS1
OUT
OUT
PWR
IN
OUT
24 MHz floppy disk clock output.
BUS clock output.
ANALOG GROUND.
OUTPUT ENABLE. Tristates all outputs when low.*
BUS clock output.
12
GND
PWR Digital GROUND.
13
CPU0
OUT CPU clock output.
14
CPU1
OUT CPU clock output.
15
PD#
IN
Power-down input shuts off both PLL stages when low.*
16
AVDD
PWR ANALOG power supply.
17
BUS2
OUT CPU clock output.
18
BUS3
OUT BUS clock output.
19
GND
PWR Digital GROUND.
20
VDD
PWR Digital POWER SUPPLY.
21
CPU2
OUT CPU clock output.
22
BUS4
OUT BUS clock output.
23
FS1
IN
Clock frequency select #1.*
24
FS0
IN
Clock frequency select #0.*
* Input pin has internal pull-up to VDD.
2
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