MD82C288-10 查看數據表（PDF） - Intel

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MD82C288-10

BUS CONTROLLER FOR M80286 PROCESSORS

Intel 

M82C288

Table 1 Pin Description

The following pin function descriptions are for the M82C288 bus controller

Symbol Type

Name and Function

CLK

I SYSTEM CLOCK provides the basic timing control for the M82C288 in an M80286

microsystem Its frequency is twice the internal processor clock frequency The falling edge

of this input signal establishes when inputs are sampled and command and control outputs

change

S0 S1

I BUS CYCLE STATUS starts a bus cycle and along with M IO defines the type of bus

cycle These inputs are active LOW A bus cycle is started when either S1 or S0 is sampled

LOW at the falling edge of CLK Setup and hold times must be met for proper operation

M80286 Bus Cycle Status Definition

M IO S1 S0

Type of Bus Cycle

0 0 0 Interrupt Acknowledge

0 0 1 I O Read

0 1 0 I O Write

0 1 1 None Idle

1 0 0 Halt or Shutdown

1 0 1 Memory Read

1 1 0 Memory Write

1 1 1 None Idle

M IO

I MEMORY OR I O SELECT determines whether the current bus cycle is in the memory

space or I O space When LOW the current bus cycle is in the I O space Setup and hold

times must be met for proper operation

MB

I MULTIBUS MODE SELECT determines timing of the command and control outputs When

HIGH the bus controller operates with MULTIBUS I compatible timings When LOW the

bus controller optimizes the command and control output timing for short bus cycles The

function of the CEN AEN input pin is selected by this signal This input is typically a

strapping option and not dynamically changed

CENL

I COMMAND ENABLE LATCHED is a bus controller select signal which enables the bus

controller to resopnd to the current bus cycle being initiated CENL is an active HIGH input

latched internally at the end of each TS cycle CENL is used to select the appropriate bus

controller for each bus cycle in a system where the CPU has more than one bus it can use

This input may be connected to VCC to select this M82C288 for all transfers No control

inputs affect CENL Setup and hold times must be met for proper operation

CMDLY

I COMMAND DELAY allows delaying the start of a command CMDLY is an active HIGH

input If sampled HIGH the command output is not activated and CMDLY is again sampled

at the next CLK cycle When sampled LOW the selected command is enabled If READY is

detected LOW before the command output is activated the M82C288 will terminate the bus

cycle even if no command was issued Setup and hold times must be satisified for proper

operation This input may be connected to GND if no delays are required before starting a

command This input has no effect on M82C288 control outputs

READY

I READY indicates the end of the current bus cycle READY is an active LOW input

MULTIBUS I mode requires at least one wait state to allow the command outputs to

become active READY must be LOW during reset to force the M82C288 into the idle state

Setup and hold times must be met for proper operation The M82C284 drives READY LOW

during RESET

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