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STV8162D(2009) 查看數據表(PDF) - STMicroelectronics

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STV8162D Datasheet PDF : 14 Pages
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STV8162
4
Application diagrams
Figure 4. Reset diagram
OUTPUT1
VREF + a
-
REG
VREF = 2.5 V
Application diagrams
10 µA
3
Ce
-b
+
VREF 0.6V
RESET
Figure 5. Internal reset diagram
VOUT1
) K
t(s VO1RST
VRTH
Produc RESET
lete K = Actual Value of VOUT1
Power On tRD
tRD
Power Off
bso Figure 6. STV8162 typical application
) - O C1 to C6 = 10 µF
Product(s VIN1
teVIN2
leVIN3
1
RESET
Ce 0.1 µF
2
DELAY
CAPACITOR
4 INPUT1
7 INPUT2
9 INPUT3
OUTPUT1 3
OUTPUT2 5
OUTPUT3 8
VOUT1
VOUT2
VOUT3
Obso C1
C2
C3
GROUND DISABLE
NC
6
10
11
C4
C5
C6
7/14

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