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STW5095 查看數據表(PDF) - STMicroelectronics

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STW5095 Datasheet PDF : 73 Pages
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STw5095
1
Overview
Overview
The STw5095 control registers are accessed through a selectable I2C-bus compatible or SPI
compatible interface.
The STw5095 asynchronous stereo audio CODEC is designed to easily fit in most audio
systems because it supports an extended master clock range (any value between 4 MHz
and 32 MHz) and at the same time it supports any audio data rate (independent in AD and
DA paths) from 8 kHz to 48 kHz and from 88 kHz to 96 kHz, moreover it can tolerate jitter on
audio data without degrading performance. The audio data serial interfaces (for AD and DA)
can be Master or Slave, are I2S compatible and they support other formats that can easily
interface to standard serial ports. The two audio interfaces can be used as a single
bidirectional interface. Two frequency programmable clock sources are available to generate
the master clock for the audio sub-system of other devices. The internal D to A and A to D
converters work with up to 24 bit resolution.
The supply voltage can be the same for the whole device, in the range 2.4 V to 2.7 V, or it
can be differentiated for digital (VCC: 1.8 V to 2.7 V), analog (VCCA: 2.4 V to 3.3 V) and
loudspeaker driver (VCCLS: VCCA to 5.5 V) to obtain best performance and maximum power
to the loudspeaker (up to 500 mW).
STw5095 has multiple analog mixable inputs and outputs. It can directly drive Stereo
Headphones without external capacitors and it has a Loudspeaker driver that can also be
used for monophonic group listening. Stereo differential and single ended microphones,
auxiliary line in stereo and mono signals can be mixed and connected to the ADC or directly
to the drivers, mixed also with DAC audio signals.
STw5095 stereo audio Codec main applications include multimedia handheld devices such
as cellular phones with added low-power high-quality MP3 andor FM radio
listening/recording features, or any battery powered equipment such as PDAs, Camcorders,
etc. that require Stereo Audio Codec with Headphones drivers.
Figure 1. Pin configuration (top view)
GND
SCLK AD_OCK DA_OCK AD_CK AMCK AD_SYNC DA_DATA
A
HDET VCCA
VCC SDA/SDIN DA_CK AD_DATA DA_SYNC IRQ
B
AUX1L MICLN VCCA CMOD AS/CSB VCC
GND MBIAS
C
CAPMIC MICLP AUX3L GNDA VCCIO VCCA MICRN AUX1R
D
AUX2LN AUX2LP LINEINL CAPLS AUX3R GNDA CAPLINEIN MICRP
E
OLN GNDCM VCMHPS LSPS LSNS LINEINR AUX2RP AUX2RN
F
OLP
GNDP VCMHP LSP
LSN
VCCP GNDP
ORN
G
VCCP
HPL
VCCLS GNDP GNDP VCCLS HPR
ORP
H
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