SX1235IMLTRT 查看數據表（PDF） - Semtech Corporation

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SX1235IMLTRT

EN300 220 Category 1 Compliant Transceiver

Semtech Corporation 

SX1235

WIRELESS & SENSING

DATASHEET

List of Figures

Figure 1. Block Diagram .............................................................................................................................................. 10

Figure 2. Pin Diagram .................................................................................................................................................. 11

Figure 3. Marking Diagram .......................................................................................................................................... 11

Figure 4. SAW Filter Performance Mask for Guaranteed Category 1 Compliance. .................................................... 14

Figure 5. Measurement configuration used for testing of the SX1235 reference design. ............................................ 15

Figure 6. Circuit schematic of the SX1235 reference design used for regulatory testing. ........................................... 16

Figure 7. SX1235 Reference Design PCB Layout, Gives both +20 dBm RF Output Tx and Category 1 Rx. ............. 17

Figure 8. Simplified SX1235 Block Schematic Diagram .............................................................................................. 22

Figure 9. TCXO Connection ........................................................................................................................................ 24

Figure 10. Typical Phase Noise Performances of the Low Consumption and Low Phase Noise PLLs. ..................... 25

Figure 11. RF Front-end Architecture Shows the Internal PA Configuration. ............................................................. 27

Figure 12. Receiver Block Diagram ............................................................................................................................. 32

Figure 13. AGC Steps Definition ................................................................................................................................. 33

Figure 14. OOK Peak Demodulator Description .......................................................................................................... 35

Figure 15. Floor Threshold Optimization ..................................................................................................................... 36

Figure 16. Bit Synchronizer Description ...................................................................................................................... 37

Figure 17. FEI Process ................................................................................................................................................ 38

Figure 18. Temperature Sensor Response ................................................................................................................. 41

Figure 19. Startup Process .......................................................................................................................................... 42

Figure 20. Time to Rssi Sample .................................................................................................................................. 44

Figure 21. Tx to Rx Turnaround .................................................................................................................................. 44

Figure 22. Rx to Tx Turnaround .................................................................................................................................. 44

Figure 23. Receiver Hopping ....................................................................................................................................... 45

Figure 24. Transmitter Hopping ................................................................................................................................... 45

Figure 25. Timer1 and Timer2 Mechanism .................................................................................................................. 50

Figure 26. Sequencer State Machine .......................................................................................................................... 51

Figure 27. SX1235 Data Processing Conceptual View ............................................................................................... 52

Figure 28. SPI Timing Diagram (single access) .......................................................................................................... 53

Figure 29. FIFO and Shift Register (SR) ..................................................................................................................... 54

Figure 30. FifoLevel IRQ Source Behavior .................................................................................................................. 55

Figure 31. Sync Word Recognition .............................................................................................................................. 56

Figure 32. Continuous Mode Conceptual View ........................................................................................................... 58

Figure 33. Tx Processing in Continuous Mode ............................................................................................................ 58

Figure 34. Rx Processing in Continuous Mode ........................................................................................................... 59

Figure 35. Packet Mode Conceptual View ................................................................................................................... 60

Figure 36. Fixed Length Packet Format ...................................................................................................................... 61

Figure 37. Variable Length Packet Format .................................................................................................................. 62

Figure 38. Unlimited Length Packet Format ................................................................................................................ 62

Figure 39. Manchester Encoding/Decoding ................................................................................................................. 66

Figure 40. Data Whitening Polynomial ........................................................................................................................ 67

Figure 41. POR Timing Diagram ................................................................................................................................. 85

Rev 1 - December 2012

Page 6

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