CMX602BP3 查看數據表（PDF） - MX-COM Inc
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CMX602BP3 Datasheet PDF : 22 Pages
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Calling Line Identifier plus Call Waiting (Type II)
4
2. Signal List
CMX602B PRELIMINARY INFORMATION
Pin No. Signal
1
XTAL
2 XTAL
3 RD
4 RT
5 AMPOUT
6 IN -
7 IN +
8
VSS
9
VBIAS
10 MODE
11 ZP
12 IRQ
13 DET
14 RXCLK
15 RXD
16 VDD
Type
Description
output Output of the on-chip Xtal oscillator inverter
input
input
(S)
input /
output
output
input
input
power
Input to the on-chip Xtal oscillator inverter
Input to the Ring or Line Polarity Reversal Detector
Open-drain output and Schmitt trigger input forming part of the Ring or Line
Polarity Reversal detector. An external resistor to VDD and a capacitor to
VSS should be connected to RT to filter and extend the RD input signal
Output of the on-chip Input Signal Amplifier
Inverting input to the on-chip Input Signal Amplifier
Non-inverting input to the on-chip Input Signal Amplifier
Negative supply
output
input
(S)
input
(S)
output
output
input
output
power
Internally generated bias voltage, held at VDD/2 when the device is not in
'Zero-Power' mode. Should be bypassed to VSS by a capacitor mounted
close to the device pins.
Input used to select the Tone Alert or FSK Level Detection operating mode.
See Section 4.1
High level on this input selects 'Zero-Power' mode, a low level input enables
the VBIAS supply, the Input signal amplifier, the Bandpass Filter , and either
the FSK or the Tone alert circuits depending on the MODE input
Open-drain output (active low) that may be used as an Interrupt Request /
Wake-up input to the associated µC. Indicates CAS Dual Tone event of
correct duration when device is in Tone Alert Detect Mode. An external pull-
up resistor should be connected between this output and VDD.
Logic level output driven by the Ring or Line Polarity Reversal Detector, the
Tone Alert Detector or the FSK Level detect circuits, depending on the
operating mode. When device is in Tone Alert Mode, it may be used as a
near end voice mute control signal. See Section 4.1
Logic level input, which may be used to clock, received data bits out of the
FSK Data Retiming block. When held high disables FSK Data Retiming
block.
Logic level output carrying either the raw output of the FSK Demodulator or
re-timed 8-bit characters depending on the state of the RXCLK input. See
Section 4.6
Positive supply. Levels and thresholds within the device are proportional to
this voltage. Should be bypassed to VSS by a capacitor mounted close to the
device pins.
Notes: input (S) = Schmitt trigger input
Table 1 : Signal List
2000 MX-COM, Inc
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480204.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA All trademarks and service marks are held by their respective companies.
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