LH5481 查看數據表（PDF） - Sharp Electronics

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LH5481

Cascadable 64 × 8 FIFO Cascadable 64 × 9 FIFO

Sharp Electronics 

LH5481/91

64 × 8 / 64 × 9 FIFO

SI

INPUT

CONTROL

IR

LOGIC

(LH5491) DI0 - DI8

(LH5481) DI0 - DI7

DATA IN

MR

MASTER

RESET

WRITE POINTER

WRITE MULTIPLEXER

MEMORY ARRAY

READ MULTIPLEXER

READ POINTER

ALMOST-FULL/

ALMOST-EMPTY

HALF-FULL

...

DATA OUT

OUTPUT

CONTROL

LOGIC

Figure 3. LH5481/91 Block Diagram

AFE

HF

... DO0

DO7

DO8

(LH5491)

OE

(LH5481)

OR

SO

5481-3

PIN DESCRIPTIONS

PIN

PIN TYPE *

DESCRIPTION

DI0 – DI7

I

Data Inputs, LH5481

DO0 – DO7

O/Z

Data Outputs, LH5481

DI0 – DI8

I

Data Inputs, LH5491

DO0 – DO8

O

Data Outputs, LH5491

SI

I

Shift In

SO

I

Shift Out

IR

O

Input Ready

OR

O

Output Ready

* I = Input, O = Output, Z = High-Impedance, V = Power Voltage Level

PIN

HF

AFE

MR

OE

VCC

VSS

PIN TYPE *

O

O

I

I

V

V

DESCRIPTION

Half-Full Flag

Almost-Full / Almost-

Empty

Master Reset

Output Enable

(LH5481 only)

Positive Power Supply

Ground

2

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