LH5481 查看數據表（PDF） - Sharp Electronics

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LH5481

Cascadable 64 × 8 FIFO Cascadable 64 × 9 FIFO

Sharp Electronics 

LH5481/91

64 × 8 / 64 × 9 FIFO

OPERATIONAL DESCRIPTION

Unlike earlier versions of FIFOs, the LH5481 and

LH5491 use dual-port Random-Access-Memory, write

and read pointers, and special control logic. The write

pointer is incremented by the falling edge of the Shift In

(SI) signal, while the read pointer is incremented by the

falling edge of the Shift Out (SO) signal. The Input Ready

(IR) signal enables data writing to the FIFO. The Output

Ready (OR) signal indicates valid read information is

available on the Data Output (DO) pins.

Resetting The FIFO

The FIFO must be reset, upon power-up, using the

Master Reset (MR) signal. This causes the FIFO to enter

an empty state,indicated by the Output Ready (OR) being

LOW and Input Ready (IR) being HIGH. All Data Output

(DO) pins will be LOW in this state. The AFE flag will be

HIGH, and the HF flag will be LOW.

If Shift In (SI) is HIGH, when the Master Reset (MR)

signal is ended, then the data on the Data Input (DI) pins

will be written into the FIFO, and Input Ready (IR) will

return LOW until Shift In (SI) is brought LOW.

If Shift In (SI) is LOW when the Master Reset (MR) is

deasserted, then Input Ready (IR) goes HIGH, but the

data on the Data Input (DI) pins does not enter the FIFO

until Shift In (SI) goes HIGH.

Shifting Data In

Data Input (DI) is shifted into the FIFO on the rising

edge of Shift In (SI). This loads input data into the FIFO,

and causes Input Ready (IR) to go LOW. When a falling

edge of Shift In (SI) occurs,the write pointer increments

to the next word position, and Input Ready (IR) goes

HIGH, indicating that the FIFO is ready to accept new

data. When the FIFO is full, Input Ready (IR) remains

LOW after the negative edge of Shift In (SI) signal; Shift

Out (SO) action is required to unload a word of data and

bring Input Ready (IR) HIGH. (See ‘Bubblethrough Con-

dition’ description.)

Shifting Data Out

Data is shifted out of the FIFO on the falling edge of

Shift Out (SO). The read pointer increments to the next

word location; FIFO data, if present, appears on the Data

Output (DO) pins; and the Output Ready (OR) signal goes

HIGH. If FIFO data is not present, Output Ready (OR)

stays LOW, indicating that the FIFO is empty; in this case,

the last valid data read from the FIFOremains on the Data

Output (DO) pins. When the FIFO is not empty, Output

Ready (OR) goes LOW after the rising edge of Shift Out

(SO).The previous data remains on the Data Output(DO)

pins until a falling edge of Shift Out (SO).

Fallthrough Condition

When the FIFO is empty, a data word entering through

the Shift In (SI) action follows one of two sequences.

If Shift Out (SO) is LOW, the data propagates to the

Data Output (DO) pins; and Output Ready (OR) goes

HIGH and stays HIGH until the next rising edge of Shift

Out (SO).

If Shift Out (SO) is held HIGH while data is shifted into

an empty FIFO as occurs in depth cascading of FIFOs,

data propagates to the Data Output (DO) pins, and Output

Ready (OR) pulses HIGH for a minimum time duration

specified by tPOR and then goes back LOW again. The

stored word remains on the Data Output (DO) pins. If

more words are written into the FIFO, they line up behind

the first word, and do not appear on the Data Output (DO)

pins until Shift Out (SO) has returned LOW.

Bubblethrough Condition

When the FIFO is full, Shift Out (SO) action initiates

one of the following two sequences:

If Shift In (SI) is LOW, Input Ready (IR) goes HIGH and

stays HIGH until the next rising edge of Shift In (SI).

If Shift In (SI) is held HIGH while data is shifted out of

a full FIFO, as occurs in depth cascading of FIFOs, Input

Ready (IR) pulses HIGH for a minimum time duration

specified by tPIR, and then goes back LOW again. Special

Data Input (DI) setup and hold times (tSIR and tHIR,

respectively) are defined for this condition.

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