T35L3232B 查看數據表（PDF） - Taiwan Memory Technology
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T35L3232B Datasheet PDF : 19 Pages
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tm TE
CH
PIPELINE READ TIMING
Preliminary T35L3232B
CLK
ADSP
ADSC
ADDRESS
GW, BWE,
BW 1- B W4
CE
(NOTE2)
ADV
OE
Q
t KC
t KH t KL
t ADSS t ADSH
t ADSS t ADSH
t AS t AH
A1
A2
t WS t WH
t CES t CEH
A3
Burst continued with
new base address.
Deselect cycle.
t AAS t AAH
ADV suspends burst.
(NOTE3)
t KQLZ
tOEHZ
t OEQ
tOELZ
t KQ
t KQX
Hig h -Z
t KQ
Q(A1)
Q(A2)
(NOTE1)
Q(A2+1)
Sing le READ
Q(A2+2)
Q(A2+3)
BURST READ
t KQHZ
t KQX
Q(A2)
Q(A2+1)
Q(A3)
Burst wraps around
to its inital state.
DON'T CARE
UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is LOW
and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE
does not cause Q to be driven until after the following clock rising edge.
Taiwan Memory Technology, Inc. reserves the right P. 12
to change products or specifications without notice.
Publication Date: FEB. 2000
Revision:0.A
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