T35L3232B 查看數據表（PDF） - Taiwan Memory Technology
零件编号
产品描述 (功能)
生产厂家
T35L3232B Datasheet PDF : 19 Pages
| |||
tm TE
CH
WRITE TIMING
CLK
t KC
t KH t KL
t ADSS t ADSH
ADSP
ADSC
t ADSS t ADSH
t AS t AH
ADDRESS
BWE,
BW1-BW4
A1
A2
BYTE WRITE signals are
ignored for first cycle when
ADSP initialtes burst.
GW
CE
(NOTE2)
t CES t CEH
ADV
OE
(NOTE3)
t DS t DH
(NOTE4)
Preliminary T35L3232B
ADSC extends burst.
t ADSS t ADSH
t WS t WH
(NOTE5)
A3
t WS t WH
ADV suspnds burst.
t AAS t AAH
D
Hig h-Z
D(A1)
tOEHZ
Q
BURST READ
Single WRITE
D(A2)
D(A2+1)
(NOTE1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1) D(A3+2)
BURST WRITE
Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst
address following A2.
2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is
LOW and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.
3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time.
This prevents input/output data contention for the time period to the byte write enable inputs being
sampled.
4. ADV must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4
LOW.
Taiwan Memory Technology, Inc. reserves the right P. 14
to change products or specifications without notice.
Publication Date: FEB. 2000
Revision:0.A
Share Link: 