T35L3232B 查看數據表（PDF） - Taiwan Memory Technology

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T35L3232B

SYNCHRONOUS BURST SRAM 32K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

PIPELINE READ/WRITE TIMING

Preliminary T35L3232B

CLK

ADSP

t KC

t KH t KL

t ADSS t ADSH

ADSC

t AS t AH

ADDRESS A1

A2

BWE

BW 1- B W4

CE

(NOTE2)

t CES t CEH

A3

A4

t WS t WH

A5

A6

ADV

OE

D

Q

t KQ

t DS t DH

Hig h -Z

t KQLZ

Hig h -Z

Q(A1)

tOEHZ

D(A3)

Q(A2)

tOELZ

t KQ

Q(A3)

(NOTE1)

Q(A4)

Q(A4+1)

Q(A4+2) Q(A4+3)

Back-to-Back READs

Single WRITE

Pass- throu gh

READ

BURST READ

D(A5)

D(A6)

Back-to-Back

WRITEs

DON'T CARE

UNDEFINED

Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst

address following A4.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW, CE2 is

LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP , ADSC or ADV

cycle is performed.

4. GW is HIGH.

5. Back-to-back READs may be controlled by either ADSP or ADSC.

Taiwan Memory Technology, Inc. reserves the right P. 15

to change products or specifications without notice.

Publication Date: FEB. 2000

Revision:0.A

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