T5743 查看數據表（PDF） - Atmel Corporation

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T5743

UHF ASK/FSK Receiver

Atmel Corporation 

RF Front-end

4 T5743

The RF front-end of the receiver is a heterodyne configuration that converts the input

signal into a 1 MHz IF signal. According to Figure 3, the front-end consists of an LNA

(low-noise amplifier), LO (local oscillator), a mixer and an RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO

(crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled

oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on

the voltage at Pin LF. fLO is divided by factor 64. The divided frequency is compared to

fXTO by the phase frequency detector. The current output of the phase frequency detec-

tor is connected to a passive loop filter and thereby generates the control voltage VLF for

the VCO. By means of that configuration VLF is controlled in a way that fLO/64 is equal to

fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO/64.

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crys-

tal. According to Figure 4, the crystal should be connected to GND via a capacitor CL.

The value of that capacitor is recommended by the crystal supplier. The value of CL

should be optimized for the individual board layout to achieve the exact value of fXTO and

hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy

of the crystal and the XTO must be considered.

Figure 4. PLL Peripherals

VS

DVCC

CL

XTO

LFGND

LF

R1 = 820 W

C9 = 4.7 nF

C10 = 1 nF

VS

LFVCC

R1

C10

C9

The passive loop filter connected to Pin LF is designed for a loop bandwidth of

BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of

the LO. Figure 4 shows the appropriate loop filter components to achieve the desired

loop bandwidth. If the filter components are changed for any reason please notify that

the maximum capacitive load at Pin LF is limited. If the capacitive load is exceeded, a bit

check may no longer be possible since fLO cannot settle in time before the bit check

starts to evaluate the incoming data stream. Self polling does therefore also not work in

that case.

fLO is determined by the RF input frequency fRF and the IF frequency fIF using the follow-

ing formula: fLO = fRF - fIF

To determine fLO, the construction of the IF filter must be considered at this point. The

nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter’s corner fre-

quencies, the filter is tuned by the crystal frequency fXTO. This means that there is a

fixed relation between fIF and fLO. This relation is dependent on the logic level at Pin

MODE.

4569A–RKE–12/02

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