T87C5101
T83C5101/02
8-bit Low pin count Microcontrollers, 0-66 MHz
1. Description
TEMIC T8xC5101/02 family is a high performance
CMOS ROM, OTP, EPROM derivative of the 80C51
CMOS single chip 8-bit microcontroller.
The T8xC5101/02 family is a low pin count device
where only Port 1, port 3 and 2/6 bits of a new port 4
are outputted. This prevents to do any external access,
like external program memory access (fetch, MOVC) or
external data memory (MOVX)
The T8xC5101/02 family retains all features of the
TEMIC 80C51 with extended capacity 8Kb ROM (5102),
16Kb ROM (5101) / 16Kb EPROM/OTP (5101) , 256
bytes of internal RAM, a 6-source, 4-level interrupt
system, an on-chip oscillator and three timer/counters.
In addition, the T8xC5101/02 family has an XRAM of
256 bytes, the X2 feature, a more versatile serial channel
that facilitates multiprocessor communication (EUART),
a dual data pointer and an improved timer 2.
The fully static design of the T8xC5101/02 family allows
to reduce system power consumption by bringing the
clock frequency down to any value, even DC, without
loss of data.
The T8xC5101/02 family has 2 software-selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q 80C51 code Compatible
• 8051 instruction compatible
• 16 I/O + 2 Outputs in 24 pin packages
16 I/O + 6 Outputs in 28 pin packages
• Three 16-bit timer/counters
• 256 bytes scratchpad RAM
q Program Memory
• 8Kb ROM T83C5102
• 16Kb ROM T83C5101
• 16Kb EPROM/OTP T87C5101
q High-Speed Architecture
• 40 MHz from 2.7 to 5.5V, commercial or
industrial temperature range :
- 40 MHz with a 40 MHz crystal in std mode
- 40 MHz with a 20 MHz crystal in X2 mode
• 66 MHz from 4.5 to 5.5V, commercial
temperature range
- 40MHz with a 40 MHz crystal in std mode
- 66MHz with a 33MHz crystal in X2 mode
q Dual Data Pointer
q On-chip eXpanded RAM (XRAM) (256 bytes)
q Programmable Clock Out and Up/Down Timer/
Counter 2
q Asynchronous port reset
q Interrupt Structure with
• 6 Interrupt sources,
• 4 level priority interrupt system
q Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
q Low EMI (no ALE)
q Power Control modes
• Idle mode
• Power-down mode
q Packages: SO24, DIL24, TSSOP24*, SO28*
* check for availability
Rev. E - 29 February 2000
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