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TA0313

STMicroelectronics Solutions for ADSL Line Interfaces

STMicroelectronics 

STMicroelectronics Solutions for ADSL Line Interfaces

TA0313

As Vo° equals Vo without loading, the gain in this case becomes:

G = -V----o----(--n---V-o----li--o---a----d----) = -1----+-----1--2---R---R--–----1----2--RR----------+23-------RR----------23----

The gain for the loaded system will be:

Equation 1

GL = V-----o----(--w-----i-V-t--h-i---l--o---a----d----) = 12-- 1-----+-----1-2---R----R--–----1----2--RR----------+23-------RR----------23----

As shown in Figure 9, this system is an ideal generator, with a synthesized impedance equal to the

internal impedance of the system. Therefore, the output voltage becomes:

Equation 2

Vo = (ViG) – (RoIout)

with Ro the synthesized impedance and Iout the output current. On the other hand Vo can be expressed

as:

Equation 3

Vo

=

Vi1 + -2--R-R---1--2-- + RR-----23--

----------------1-----–-----RR---------23--------------------

–

-R----s----1----I--o----u---t

1 – RR-----23--

Figure 9: Equivalent schematic, where Ro is the synthesized impedance

Ro

Iout

Vi.Gi

1/2RL

By identifying of both Equation 2 and Equation 3, the synthesized impedance is, with Rs1=Rs2=Rs:

Equation 4

Ro = -----R-----s------

1 – R-----2--

R3

Unlike the level of Vo° required for passive impedance, Vo° will be smaller than 2Vo in this case. Let us

write Vo°=kVo with k the matching factor varying between 1 and 2. Assuming that the current through R3

is negligible, the resistance divider becomes:

Ro = -----k----V----o----R-----L------

RL + 2Rs1

After choosing the k factor, Rs will equal to 1/2RL(k-1).

7/9

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