CXD3029R 查看數據表（PDF） - Sony Semiconductor

零件编号

产品描述 (功能)

生产厂家

CXD3029R

CD Digital Signal Processor with Built-in Digital Servo + Shock-proof Memory Controller + Digital High & Bass Boost

Sony Semiconductor 

CXD3029R

Power Pin

supply No.

Symbol

I/O Value

Description

96 FFDR O 1, 0 Focus drive output.

97 TRDR O 1, 0 Tracking drive output.

98 TFDR O 1, 0 Tracking drive output.

99 SRDR O 1, 0 Sled drive output.

100 SFDR

Digital

101 SSTP

O 1, 0 Sled drive output.

I

Disc innermost detection signal input.

102 MDS O 1, Z, 0 Spindle drive output.

103 MDP O 1, Z, 0 Spindle motor servo control output.

104 C176 O 1, 0 176.4kHz output. 88.2kHz for quasi-double speed setting.

105 VDD2 — — Digital power supply.

106 LRCK O 1, 0 D/A interface. LR clock output f = Fs.

107 LRCKI I

D/A interface. LR clock input.

108 PCMD O 1, 0 D/A interface. Serial data output. (two’s complement, MSB first)

109 PCMDI I

D/A interface. Serial data input. (two’s complement, MSB first)

110 BCK O 1, 0 D/A interface. Bit clock output.

111 BCKI I

D/A interface. Bit clock input.

112 DVDD — — DRAM interface power supply.

2-3V 113 A3

I/F 114 A2

O 1, 0 DRAM address 3.

O 1, 0 DRAM address 2.

115 A1

O 1, 0 DRAM address 1.

116 A0

O 1, 0 DRAM address 0.

117 A10

O 1, 0 DRAM address 10.

118 A11

I/O 1, 0

DRAM address 11. Write prohibition factor is input by switching with the

command.

119 TEST3 O

Test pin. Do not connect.

120 TEST4 O

Test pin. Do not connect.

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM

signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XROF is generated when the 32K RAM exceeds the ±28 frame jitter margin.

• C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode.

• R8M is the 8.4672MHz output.

• FSTO is the 2/3 frequency-division output of the XTAI pin.

• SOUT is the serial data output inside the servo block.

• SOCK is the serial data readout clock output inside the servo block.

• XOLT is the serial data latch output inside the servo block.

–7–

Share Link: