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87C196LB 查看數據表(PDF) - Intel

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87C196LB Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AUTOMOTIVE
®
Port 2
J1850
Protocol
Handler
Watchdog
Timer
Port 6
Port 0
Enhanced
SSIO
A/D
Converter
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
Bus Control
AD15:0
Bus
Controller
Port 2
SIO
Baud-rate
Generator
Bus-Control
Interface Unit
Queue
Microcode
Engine
Source (16)
ALU
Register RAM
768 Bytes
Memory
Interface
Unit
Destination (16)
Peripheral
Transaction
Server
Interrupt
Controller
EPA
6 Capture/
Compare
Channels
2 Timers
2
Compare-only
Channels
Port 1,6
OTPROM
24 Kbytes
Two additional capture/compare channels (EPA6 and EPA7) are available as software timers.
They are not connected to package pins.
A3416-01
Figure 1. 87C196LB Block Diagram
2
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